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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.

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RE: A History of Die shrink
By Sulphademus on 12/13/2006 10:35:28 AM , Rating: 2
Back in Pentium & P2 days you were looking at 350 and 250nm. Days of most of the P4 and Athlon XP were done on the 180 scale. Later P4 and early A64 were 130. Now we are at 90 and looking to move to 65.

Remember that these are all in nm, nanometer = one billionth of a meter. Most of the P2 and earlier tech was in microns, being millionths. (nano: inverse of giga, micro: inverse of mega... so what is the inverse of tera?)

RE: A History of Die shrink
By Wonga on 12/13/2006 11:31:01 AM , Rating: 3
Pico is below nano (so I recall), if that's what you mean.

RE: A History of Die shrink
By masher2 on 12/13/2006 11:34:02 AM , Rating: 1
> "so what is the inverse of tera?..."


RE: A History of Die shrink
By Khato on 12/13/2006 11:59:14 AM , Rating: 2
Well, you actually have to go -quite- a ways back before gate lengths were in microns, P2 era is, as you said, a quarter of a micron at 250nm.

Going down, it's milli, micro, nano, pico, femto, atto. Heh, interwire capacitances at a 240nm process tech were measured in attoferads/um, though I'd imagine that now they might be higher.

RE: A History of Die shrink
By jonnybradley on 12/14/2006 3:55:53 AM , Rating: 2
Thanks guys, good info

"You can bet that Sony built a long-term business plan about being successful in Japan and that business plan is crumbling." -- Peter Moore, 24 hours before his Microsoft resignation
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