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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.

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RE: Getting a little stuffy in there....
By bobsmith1492 on 12/13/2006 7:24:10 AM , Rating: 2
Some form of nanotechnology...

Are you saying 90, 65, and 45nm processes are not "nanotechnology?" What do you think the "n" stands for?

It irks me that people think some magical "nanotechnology" will be the answer to everything. Someone did a very, very good job at marketing the term.

All one has to do is state they are researching nanotechnology and/or AI and people will just throw money at them...

By masher2 on 12/13/2006 9:08:07 AM , Rating: 2
> "Are you saying 90, 65, and 45nm processes are not "nanotechnology?"...

Well, the original definition of nanotech was manipulation of material on or about the nanometer scale (1-10nm). However, the marketing value of the buzzword took hold, people used the term loosely, and now it encompasses anything at the 100nm scale, or even larger.

RE: Getting a little stuffy in there....
By Viditor on 12/13/2006 9:40:32 AM , Rating: 2
If you're interested, there's a decent (not too technical) article here

"Researchers at IBM have overcome an important obstacle to building computers based on carbon nanotubes, by developing a way to selectively arrange transistors that were made using the carbon molecules. The achievement, described in the current issue of Nano Letters, could help make large-scale integrated circuits built out of carbon nanotubes possible, leading to ultrafast, low-power processors...
According to estimates, carbon nanotubes have the potential to produce transistors that run 10 times faster than even anticipated future generations of silicon-based devices, while at the same time using less power"

As to the actual size, I'm sorry I wasn't more specific (though masher is 100% correct), the reason is that nobody knows the actual size yet...

RE: Getting a little stuffy in there....
By Goty on 12/13/2006 7:24:12 PM , Rating: 2
Nanotubes might halpe in the area of speed, but the tubes themselves are quite large on the atomic scale.

By Goty on 12/13/2006 10:13:35 PM , Rating: 2

sorry, that was ugly. Might as well use the whole preview function as long as I'm being forced to anyways =P

"It's okay. The scenarios aren't that clear. But it's good looking. [Steve Jobs] does good design, and [the iPad] is absolutely a good example of that." -- Bill Gates on the Apple iPad
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