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Print 108 comment(s) - last by joset00.. on Dec 17 at 1:53 PM

To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.



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RE: th wonders of AMD
By Khato on 12/13/2006 1:56:20 AM , Rating: 2
Mmmmm, I don't quite remember what info on P1266 has and hasn't been released yet, going from the info on Intel's process site it isn't much. In fact, there's no mention of the tricks being implemented, just some of their results, and I'd hate to ruin a surprise.

Whereas AMD's press release today states the use of ultra-low k interconnect dielectrics and immersion lithography in their 45nm process. While the ultra-low k interconnect dielectric shouldn't pose much of a problem, I do wonder at how immersion lithography will go. After all, I don't believe that there has been any mass production with immersion lithography thus far, and I'd imagine it to require a fair bit more retooling than the norm.


RE: th wonders of AMD
By Viditor on 12/13/2006 2:08:59 AM , Rating: 2
quote:
Mmmmm, I don't quite remember what info on P1266 has and hasn't been released yet, going from the info on Intel's process site it isn't much. In fact, there's no mention of the tricks being implemented, just some of their results, and I'd hate to ruin a surprise

All that I've read so far is that they will use a new high-k metal gate that they released a white paper on a little over a year ago...
http://www.intel.com/technology/silicon/si11031.ht...


RE: th wonders of AMD
By Khato on 12/13/2006 12:06:13 PM , Rating: 2
Ahhhh, so they have released that tidbit already? You had me wondering by the comment about AMD/IBM 45nm process looking better than Intel's.

Hehe, high-k gate dielectric and metal gate electrode >> decreasing wire capacitance by a small amount and possibly etching neater lines.


RE: th wonders of AMD
By Viditor on 12/13/2006 11:59:26 PM , Rating: 2
quote:
high-k gate dielectric and metal gate electrode >> decreasing wire capacitance by a small amount and possibly etching neater lines


If that were the extent of the improvements, I would agree with you...but look again at the MASSIVE increase in PMOS and NMOS.
The new DSL process increases efficiency by as much as 80% I believe.
Don't get me wrong, Intel's high-k/metal is absolutely brilliant...and it may indeed prove to be better. At this point my GUESS is that it won't be, but that is more of a WAG than anything else.
The defect decrease from immersion will certainly help AMD's yields and should keep costs down significantly.
Either way, we are going to be seeing some awesome chips coming out over the next 2 years, and at very reasonable pricing too!


RE: th wonders of AMD
By masher2 (blog) on 12/14/06, Rating: 0
RE: th wonders of AMD
By Viditor on 12/14/2006 7:52:58 AM , Rating: 2
quote:
Its not going to reduce defect rates...in fact, the resultant increase in defect rates is one of the primary factors speaking against its use

Which is why the article on reduced defects for the IBM/AMD process is so exciting!
I seem to recall that AMD wasn't expected to be successful with SOI either...in fact Intel commented that it wasn't really possible economically until at least 45nm or below.


RE: th wonders of AMD
By Khato on 12/14/2006 1:03:48 AM , Rating: 2
Hehe, I guess that the 80% pmos/24% nmos channel drive current increase compared to unstrained transistors might be a massive increase for AMD/IBM. I'm more tempted to call it playing catch up to Intel whose strained silicon tech will be on its third process node at 45nm.

Adding greater experience in strained silicon together with the high-k gate dielectric/metal gate should result in the Intel 45nm process having even greater channel drive current than the AMD/IBM. Not to mention the fact that high-k gate dielectrics say bye bye to gate leakage.

Mmm, and I wonder how the dielectric constant of the AMD/IBM 'ultra-low-k' interconnect dielectric compares to the Intel? It's hard to say since they don't often state the actual numbers, just the results of it in comparison to another previous unknown quantity, lol.

Oh, and boo hiss to reasonable pricing! Let's get those budget machines back up over $1000 with 30% of that going to the CPU manufacturers =D


RE: th wonders of AMD
By Viditor on 12/14/2006 7:49:34 AM , Rating: 2
quote:
I'm more tempted to call it playing catch up to Intel whose strained silicon tech will be on its third process node at 45nm

It may be their 3rd node, but they still haven't been able to achieve a decent DSL...
quote:
Mmm, and I wonder how the dielectric constant of the AMD/IBM 'ultra-low-k' interconnect dielectric compares to the Intel?

I believe I read that AMD's ultra-low k is at ~2.3 for the constant. I haven't seen data on Intel yet...


And yes, as an investor in both AMD and Intel, I would sure like to see an end to this price war! :)


RE: th wonders of AMD
By joset00 on 12/16/2006 8:17:48 PM , Rating: 2
quote:
In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors .


Well noted.
I guess the statement speaks for itself; it should refer to any incremental advantage over any previous straining techniques.

quote:
Not to mention the fact that high-k gate dielectrics say bye bye to gate leakage.


Not quite. Leakage can effectively be reduced... but not avoided.

quote:
Mmm, and I wonder how the dielectric constant of the AMD/IBM 'ultra-low-k' interconnect dielectric compares to the Intel?


You mentioned it... 'ultra-low-k interconnect '. And, that's what IBM/AMD are referring to when addressing the 'big' three issues concerning process improvements, not the gate oxide itself (so much for the AMD/Intel's comparison on transistor process dielectrics...)

http://www.physorg.com/news85247225.html


Cheers!


RE: th wonders of AMD
By JumpingJack on 12/16/2006 12:04:17 AM , Rating: 2
quote:
The new DSL process increases efficiency by as much as 80% I believe.


Not hardly... AMD published 4 stressors DSL (2 of them), eSiGe, and stress memorization. Cummulative they improve PMOS 63% and NMOS 32%, the combined CMOS improvement reported by AMD is 40% (factoring inverted logic comprises a mix of NMOS and PMOS) --- and this is comparing to a transistor built without the technology, not against 90 nm, that comparison would need to be made by comparing Idsat for both at equivalent gate lengths. Even at 40%, the release 65 nm is a paultry 2.6 GHz top bin split at launch, and OC is anemic at barely 2.95 GHz stock, and 3.1 GHz (xtremesys.org/forums) using a wizz bang FX-74 cooler (which you know must be fantastic).... Suggesting the move to 65 nm helped a little in power and some in size only.

In fact, the die size of a 512x2 X2 is 112 mm^2 as reported by Semiconductor Insights (registration required), so they didn't even meet the 50% scaling factor that 90 to 65 nm should have accomplished.

AMD 65 nm is looking to be a dud.


RE: th wonders of AMD
By JumpingJack on 12/16/2006 12:08:56 AM , Rating: 2
Here is the link to the data:
http://www.realworldtech.com/page.cfm?ArticleID=RW...
4 stressors, 40% improvement over transistors without the stress -- 63% for PMOS, 32% for NMOS


"We shipped it on Saturday. Then on Sunday, we rested." -- Steve Jobs on the iPad launch

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