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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.

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GHz war part 2
By splint on 12/13/2006 12:56:40 AM , Rating: 3
The reduction on interconnect capacitance has me most excited. This along with improved dielectrics directly relates to switching speed which greatly impacts the clock frequency bottom line. I wonder, with all vendors obviously embracing short pipeline architectures for their next generation, will we finally see AMD beat out Intel again in the GHz race like the Atholons of yore? It now seems quite possible. I'm willing to bet that if they do they will drop their CPU performance rating number in a heartbeat.

RE: GHz war part 2
By splint on 12/13/2006 1:06:26 AM , Rating: 4
Remember that one of the main goals of Intel's abysmal netburst was to supplant AMD as the GHz king after their ego was crushed when AMD reached the magical "G" first. Now, since a short pipeline is the obvious choice, fab technology plays the largest role in clock speeds for the first time ever.

RE: GHz war part 2
By Khato on 12/13/2006 8:45:00 PM , Rating: 2
The reduction of interconnect capacitance is due to the improved 'ultra-low k' interconnect dielectrics. I wouldn't say that this necessarily has a direct impact on switching speed, as any good design is going to take wire models into effect on the transistor sizing/buffering. Besides, what exactly are interconnect capacitances like on the 45nm node anyway? The only numbers I know are from the outdate 240nm, at which time it was on the order of 20-50 aF/um - tiny in comparison to gate capacitance at the time. Though with the smaller dimensions I know full well that gate capacitance will have gone down and wire capacitance up.

Hehe, don't expect the reduced capacitances/increased current drive that the announced improvements offer to mean faster transistor switching though. Rather I'd expect that they'll just size things accordingly so that everything ends up the same, just taking up less space. After all, that will also reduce their leakage current by some amount, and leakage current may well be quite a problem for them.

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