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To make 45nm process manufacturing easier: just add water

Intel has said on multiple occasions that its 45nm process is on track for production 2007. In fact, Intel began sampling its Penryn 45nm chips just several weeks ago. At the IEDM, IBM and AMD described three technologies that hope to compete with Intel’s 45nm development: the use of immersion lithography, which AMD says will “deliver enhanced microprocessor design definition and manufacturing consistency,” ultra-low-K interconnect dielectrics to enhance performance-per-watt ratio and multiple enhanced transistor strain techniques.

Current process technologies use conventional lithography, which has significant limitations in defining microprocessor designs beyond the 65nm process technology generation. Immersion lithography uses a projection lens filled with purified water as part of the step-and-repeat lithography -- think of the same principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image fidelity that can improve chip-level performance and manufacturing efficiency. For example, the performance of an SRAM cell shows improvements of approximately 15 percent due to this enhanced process capability, without resorting to more costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous, ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well as lowering power dissipation. This advance is enabled through the development of an ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength. The addition of ultra-low-K interconnect provides a 15 percent reduction in wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm generation transistors, IBM and AMD demonstrated multiple enhanced transistor strain techniques that give an 80 per cent increase in p-channel transistor drive current and a 24 per cent increase in n-channel transistor drive current compared to unstrained transistors. The companies claim that their achievement results in the highest CMOS performance reported to date in a 45nm process technology.

In November 2005, AMD and IBM announced an extension of their joint development efforts until 2011 covering 32nm and 22nm process technology generations. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.

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RE: Man I need to pick up a book
By feelingshorter on 12/12/2006 11:18:40 PM , Rating: 1
I just read it and I really have no idea what they are talking about, but why worry about the detail? Just know that processors are getting faster.

RE: Man I need to pick up a book
By JumpingJack on 12/17/2006 1:52:10 AM , Rating: 2
I will add to the discussion some --- the above posts are correct in their designation. When NMOS and PMOS are manufactured into the same circuit, it is collectively called CMOS (complimentary metal oxide semiconductor). The reason is that the differential between the two makes it much easier to design inverter circuites with fewer overall transistors (i.e. flipping the logic from what I understand -- not an EE myself).

Nonetheless, from the device physics point of view, NMOS
'uses' (for lack of a better word) electrons as the majority charge carriers while PMOS has the holes (or void of e- density) as the majority carriers. People often think of holes as "postive protons" flowing, but this is not the case. Anyway, the physics of a hole traveling through the lattice is opposite (mathematically) and different than an electron in terms of lattice interactions ... ultimately this leads to slower switching PMOS transistors when compared to NMOS transistors -- i.e. NMOS transistors have shorter gate delays.

Device speed fundamentally can be observed through basic transistor parametrics, one such parametric is saturated drive current. PMOS always has lower drive current than NMOS, so technologies that can increase PMOS are always of interest --- this is why Intel implemented SiGe into their process at 90 nm and the reason AMD is trying to do so in 65 nm. SiGe provides the correct 'kind of stress' to the PMOS channel to improve the hole mobility.

"I'd be pissed too, but you didn't have to go all Minority Report on his ass!" -- Jon Stewart on police raiding Gizmodo editor Jason Chen's home
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