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Quad-core, HyperTransport 3.0 and more

AMD is expected to release its 65nm products soon. Moving beyond the 65nm Brisbane die shrink and Windsor FX, AMD has a couple of other tricks up its sleeves. AMD plans to transition from its Cities core products to new Stars cores. This transition uses AMD’s new core naming scheme. While AMD has typically named its processor cores after cities, the new naming scheme uses star names.

The Stars family includes the upcoming Agena FX, Agena, Kuma, Rana and Spica cores. AMD will be introducing plenty of architectural changes with the upcoming Stars family. Stars family processors will switch over to AMD’s previously announced HyperTransport 3.0 architecture. Previously, Star processors have been referred to as Revision H or K8L -- if that's not confusing enough, AMD calls the architecture of the Stars family Greyhound. While Stars family processors use the HyperTransport 3.0 protocol, it will be backwards compatible with HyperTransport 1.0 systems.

HyperTransport 3.0 is expected to provide twice the amount of bandwidth between the processor and chipset. It will also allow the processor and internal north bridge to operate at different frequencies as well. With HyperTransport 3.0, the north bridge can operate at 75% of the maximum clock frequency of the processor. AMD roadmaps claim the greater bandwidth of HyperTransport 3.0 is important for PCIe 2.0 and upcoming multi-GPU, integrated graphics and multiprocessor performance.

In addition to HyperTransport 3.0, Stars family processors feature a 128-bit floating point unit for each CPU core, DDR2-1066 support, SSE4A instructions and a split power plane. Split power planes allow the processor and internal north bridge to operate at different voltages and speeds. The advantages of split power planes are it allows the north bridge speed and voltage to never change during Cool’n’Quiet power saving measures. With split power planes the Stars processors require separate PLLs for the processor and internal north bridge.

Stars family processors will use socket AM2+, with the exception of the Agena FX. Nevertheless, Stars family processors will be backwards compatible on socket AM2 motherboards, though performance is sacrificed by falling back to HyperTransport 1.0. AMD's documentation no longer refers to AM3; it appears AM2+ is the expected socket AM3.

Beginning in Q3’2007 AMD is expected to release its first Stars quad-core processors. The new quad-core processors are based on AMD’s Agena and Agena FX cores. Targeting AMD’s 4x4 platform is the Agena FX core. Agena FX will only be available on Socket 1207+ and offer dual processor functionality. The vanilla Agena core will be available on single processor socket AM2+ platforms.

Agena FX and Agena based processors offer identical features. New to the Agena FX and Agena cores is a shared L3 cache. 2MB of L3 cache will be shared between all four processor cores. The L2 cache will be 2MB as well. Clock frequencies of 2.7 GHz to 2.9 GHz are initially expected. The HyperTransport 3.0 frequency for Agena FX and Agena cores is expected to be clocked at 4000 MHz. Agena FX and Agena core processors will be manufacturing using a 65nm process and carry 125W TDPs. The first Agena FX and Agena based processors are expected to arrive in Q3’2007.

AMD will be releasing new Kuma core dual-core processors in Q3’07 as well. The new Kuma core processors feature HyperTransport 3.0 clocked at 4000 MHz, 1MB of L2 cache and 2MB of shared L3 cache. Kuma processors are expected to arrive in 2.0 GHz to 2.9 GHz frequencies for socket AM2+. TDP for Kuma core processors is expected at 89W and 65W.

Single-core products won’t be left out of the Stars family either. AMD will release single-core Rana and Spica cores towards the end of 2007. Rana core processors will be replacing Orleans and Lima Athlon 64 single-core processors while Spica will be replacing single-core Venice Athlon 64 and Manilla Sempron processors. AMD’s roadmap doesn’t reveal too much on Rana and Spica. Nevertheless, Rana and Spica will feature HyperTransport 3.0 and socket AM2+ compatibility.



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RE: Hmm
By JackPack on 11/15/2006 6:47:17 AM , Rating: 4
quote:
Huh? When were they wrong on process nodes?

They were wrong almost every time. Let's look at a 2003 article: http://www.eetimes.com/story/OEG20030612S0005

AMD will bring SOI (silicon-on-insulator) technology to its microprocessors made with 90-nm design rules later this year . For the 65-nm node expected to come to manufacturing in 2005 , AMD has a goal of integrating strained silicon channels with SOI substrates

Obviously, AMD didn't have 90nm in 2003 nor 65nm in 2005. Their initial estimates have always been lofty goals that were later pushed out. You can dig back to 130nm and see the same thing.

quote:
Actually, they don't...I think you're forgetting that they are building new Fabs for those nodes (no changes needed to existing equipment, it will be new equipment).
It's the same idea. The capital needs to come from somewhere. Yes, Fab 38 is planned, but the capital isn't there, particularly after the ATi acquisition. Even with 65nm, AMD didn't have the money until Q2'06 for the equipment. If you look at AMD's 10-K filing, spending on process tech capital equipment is very much dependent upon IBM. Unless IBM is ready and willing for 45nm, it will be delayed.


RE: Hmm
By Viditor on 11/15/2006 8:46:30 AM , Rating: 3
quote:
They were wrong almost every time. Let's look at a 2003 article:

That was a mistake by EETimes (or they got confused)...AMD was solid on their 90nm shipping date of July 2004 and first production date of Dec 2003 (which is when they did indeed begin production)...this long lead time is due to:
1. AMD had only one Fab, and conversion is a slow process.
2. They needed to build up enough inventory for the launch (which was quite extensive).

Also (if you will recall) Intel did "release" 90nm in Jan of that year, but they had no inventory. In fact they had so few chips produced that Dell had to cancel all sales of Prescott systems for a whole quarter (until mid-April) until Intel could get them made.

As to 65nm, what AMD said (and most people who don't understand the semi business don't get this) was that they would begin production of 65nm in Aug 2006...in fact they began in June/July.

I challenge you to find any quote from AMD that agrees with what EETimes "reported".

quote:
Yes, Fab 38 is planned, but the capital isn't there, particularly after the ATi acquisition


Sure it is! In fact, once again Dresden agreed to subsidise the funding quite some time ago. All of the future expense of Fab 38 is already locked in (in fact that was a condition of the Morgan-Stanley loan for ATI, listed in the 10-Q).
quote:
If you look at AMD's 10-K filing, spending on process tech capital equipment is very much dependent upon IBM

Huh? I have no idea what you mean here...could you give me a clue what section of the (I assume you meant 10-Q and not the 8-K) you are referring to?
As AMD is the co-developer of the process (it's not IBM's process alone), and AMD is installing their own solely owned lines, I fail to see what IBM has to do with 45nm at all (except that they also have rights to the process).
Even though it was developed at IBM's Fab in East Fishkill, AMD had paid for half the cost of the equipment in that Fab as part of their original deal...


"It seems as though my state-funded math degree has failed me. Let the lashings commence." -- DailyTech Editor-in-Chief Kristopher Kubicki

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