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Patent infringement suits ramp up for the holiday season

In what appears to be a bit of a shocker in the industry, Silicon Graphics Inc. this week filed a patent infringement lawsuit against ATI Technologies Inc. Current details on the patent infringement is short but SGI is claiming that ATI infringed on SGI U.S. Patent No. 6,650,327, which covers some technical aspect of graphics processing. Details on what exactly the patent is about was also omitted.

Silicon Graphics Inc. (SGI) is also seeking damages at an unspecified amount and an injunction, stopping ATI from developing and shipping graphics processors that infringe on SGI's patents. At this time, it's not clear what ATI has done, or if ATI will respond with its own lawsuit since both companies have been developing graphics technologies for quite a number of years.

"The Company's technology covered by the '327 patent is an important resource in achieving enhanced graphics processing demanded by today's computer systems," said Dennis McKenna, chief executive officer of Silicon Graphics. The company also indicated that whatever patent 327 was, it also licensed it for use with a number of ATI's competitors -- although the company did not indicate which companies were using the patent.

ATI itself recently completed the final stages of its merger with AMD. ATI shareholders approved of the merger in a recent meeting and both companies are now one. Neither AMD nor it's ATI division had anything to say about SGI's lawsuit.


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here are the claims of the patent at issue
By patentman on 10/25/2006 8:14:57 PM , Rating: 2
See the topic. Note that the thing claimed is a computer system and a method, NOT an algorhythm.

What is claimed is:

1. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; wherein the rasterization circuit performs scan conversion on vertices having floating point color values.

2. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; a texture circuit coupled to the rasterization circuit that applies a texture to the primitive, wherein the texture is specified by floating point values; and a texture memory coupled to the texture circuit that stores a plurality of textures in floating point values.

3. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; wherein the floating point format is comprised of sixteen bits in a s10e5 format.

4. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; and a fog circuit coupled to the rasterization circuit for performing a fog function, wherein the fog function operates on floating point color values.

5. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; and a blender coupled to the rasterization circuit which blends floating point color values.

6. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; and logic coupled to the rasterization circuit which performs per-fragment operations on floating point color values.

7. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on a floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of color values; and a display screen coupled to the frame buffer for displaying an image according to the color values stored in the frame buffer; wherein the processor, the rasterization circuit, and the frame buffer are on a single semiconductor chip.

8. The computer system of claim 7, wherein the processor, the rasterization circuit, and the frame buffer reside on a same substrate of the single semiconductor chip.

9. In a computer system, a method for rendering a three-dimensional image for display, comprising the steps of: performing geometric calculations on a plurality of vertices of a plurality of polygons; scan converting a plurality of pixels according to the vertices, wherein scan conversion is performed on floating point color values; applying a texture to the image by reading floating point texture values stored in a texture memory; simulating fog effects, wherein fog is simulated by modifying floating point color values; drawing the image for display on a display screen coupled to the computer system.

10. The method of claim 9, wherein the floating point values are comprised of sixteen bits.

11. The method of claim 10, wherein the floating point values are specified by a s10e5 format.

12. The method of claim 10 further comprising the step of storing the floating point color values in a frame buffer.

13. The method of claim 10 further comprising the step of blending at least two floating point color values.

14. The method of claim 10 further comprising the step of performing antialiasing on floating point color values.

15. The method of claim 10 further comprising the steps of: reading data from the frame buffer; modifying the data; writing modified data back to the frame buffer.

16. The method of claim 10 further comprising the step of modifying color values for lighting, wherein lighting calculations operate on floating point color values.

17. In a computer system, a method for operating on data stored in a frame buffer, comprised of: storing the data in the frame buffer in a floating point format; reading the data from the frame buffer in the floating point format; operating directly on the data in the floating point format; and writing the data to the frame buffer in the floating point format; wherein the steps of writing, storing, and reading the data in the frame buffer in the floating point format are further comprised of a specification of the floating point format, wherein the specification corresponds to a level of range and precision.

18. The method of claim 17 wherein the specification is comprised of 16 bits of data and the data are comprised of one sign bit, ten mantissa bits, and five exponent bits.

19. The method of claim 17 wherein the specification is comprised of 17 bits of data and the data are comprised of one sign bit, 11 mantissa bits, and five exponent bits.

20. The method of claim 17 wherein the specification is comprised of 16 bits of data and the data are comprised of ten mantissa bits, and six exponent bits.

21. The method of claim 17 wherein the specification is comprised of 32 bits of data and the data are comprised of one sign bit, 23 mantissa bits, and eight exponent bits.

22. A computer system having a floating point frame buffer for storing a plurality of floating point color values; wherein the floating point color values are written to, read from, and stored in the frame buffer using a specification of the floating point color values that corresponds to a level of range and precision.

23. The computer system of claim 22, wherein the floating point color values are comprised of 16 bits of data and the data are comprised of one sign bit, ten mantissa bits, and five exponent bits.

24. The computer system of claim 22, wherein the floating point color values are comprised of 17 bits of data and the data are comprised of one sign bit, 11 mantissa bits, and five exponent bits.

25. A computer system, comprising: a processor for performing geometric calculations on a plurality of vertices of a primitive; a rasterization circuit coupled to the processor that rasterizes the primitive according to a rasterization process which operates on an s10e5 floating point format; a frame buffer coupled to the rasterization circuit for storing a plurality of s10e5 floating point color values; a display screen coupled to the frame buffer for displaying an image according to the s10e5 color values stored in the frame buffer.

26. The computer system of claim 25 further comprising: a texture circuit coupled to the rasterization circuit that applies a texture to the primitive, wherein the texture is specified by s10e5 floating point values.

27. The computer system of claim 25 further comprising a lighting circuit coupled to the rasterization circuit for performing a lighting function, wherein the lighting function executes on s10e5 floating point color values.

28. The computer system of claim 25 further comprising a fog circuit coupled to the rasterization circuit for performing a fog function, wherein the fog function operates on s10e5 floating point color values.

29. The computer system of claim 25 further comprising an antialiasing circuit coupled to the rasterization circuit which performs an antialiasing algorithm on s10e5 floating point color values.

30. The computer system of claim 25 further comprising a blender coupled to the rasterization circuit which blends s10e5 floating point color values.

31. The computer system of claim 25 further comprising logic coupled to the rasterization circuit which performs per-fragment operations on s10e5 floating point color values.




By mindless1 on 10/26/2006 9:16:43 AM , Rating: 1
URLs are your friend, no need to post all this, twice.


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