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A quick list of new SSE instructions - Image courtesy HotHardware
Fourth generation streaming SIMD extensions

With Intel’s Conroe Core 2 Duo launch in June 2006, Intel added several new SSE optimizations. The new SSE optimizations included with Intel’s Core 2 architecture sped up SSE, SSE2 and SSE3 operations two-fold. This was performed by optimizing the Core 2 architecture to execute a 128-bit SSE, SSE2 and SSE3 instruction in a single clock cycle. Intel’s previous Netburst and Core architecture required two clock cycles to execute the same instruction. These extensions and optimizations of SSE3 were not actually new instructions but more or less an improvement in efficiency.

Intel’s Pat Gelsinger announced today that Intel has published the white paper on its SSE4 instructions that will appear in its next-generation 45nm products. The new SSE4 instructions add 50 new performance enhancing instructions. These instructions optimize vector compiling, media, string and text processing and application targeted accelerators.

The Core architecture implemented on the Core 2 Duo processors added 32 additional supplimental streaming instructions to SSE3.  These instructions, dubbed Supplimental Streaming SIMD, are not SSE4 and should not be confused as such.

SSE4 instructions are expected to arrive incrementally in Intel’s first 45nm product that is expected to sample in the second half of 2007. This includes Intel’s upcoming Nehalem, which will be Intel’s second generation Core architecture, and Penryn, a 45nm shrink of Core 2 Duo. Intel Penryn and other 45nm processors are expected to begin sampling the second half of 2007 and begin shipping in the first half of 2008.  Full implementation of SSE4 is only planned for Nehalem at this time.

More details are available in Intel's whitepaper on the subject.

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lol, CRC32 instruction
By Tyler 86 on 9/28/2006 4:42:40 AM , Rating: 2
About time...

This particular instruction might be reverse-implementable on current applications that use common CRC32 implementations..

mov rax, esp
mov rcx, rsp+100h
call crc32
... more than enough instructions, I'm sure...

all to
crc32 esp, rsp+100h

Why, a nice little shell script could do it...
Might help substantially in video-game network, where quick verification of packet integrity is of great importance...

RE: lol, CRC32 instruction
By Tyler 86 on 9/28/2006 4:46:08 AM , Rating: 2
...erm, esp being an assumption that the stack pointer is low (>=(1<<31)) due to the application being loaded, and crc32 accepting a 'near' address, on an amd64 system... shrug.

actually, it's still quite ridiculous, but hey, it's an example...

RE: lol, CRC32 instruction
By Visual on 9/29/2006 5:40:00 AM , Rating: 2
a dedicated instruction will save you almost nothing in my oppinion - the cpu still has to do pretty much the same operations, no matter if you code it with just one asm instruction that gets broken to dozens of uops.
also, i kinda doubt the instruction will be suitable for all possible scenarios... i.e. it may work if you need to verify certain data at once, but what if you want to do it incrementally, your data isn't linear, or something like that?
and specifically for videogame networking, error checking (and correction) is better done with more traditional algorythms - parity bits, etc. since the packets are quite small.

its good to see new and new instructions, but i think this is getting somewhat ridiculous. soon we'll have a separate asm instruction for every imaginable function from the c++ standard libraries :p

btw, i wonder... is it possible to compile programs to uops, or to program in uops directly?

"Intel is investing heavily (think gazillions of dollars and bazillions of engineering man hours) in resources to create an Intel host controllers spec in order to speed time to market of the USB 3.0 technology." -- Intel blogger Nick Knupffer
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