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A quick list of new SSE instructions - Image courtesy HotHardware
Fourth generation streaming SIMD extensions

With Intel’s Conroe Core 2 Duo launch in June 2006, Intel added several new SSE optimizations. The new SSE optimizations included with Intel’s Core 2 architecture sped up SSE, SSE2 and SSE3 operations two-fold. This was performed by optimizing the Core 2 architecture to execute a 128-bit SSE, SSE2 and SSE3 instruction in a single clock cycle. Intel’s previous Netburst and Core architecture required two clock cycles to execute the same instruction. These extensions and optimizations of SSE3 were not actually new instructions but more or less an improvement in efficiency.

Intel’s Pat Gelsinger announced today that Intel has published the white paper on its SSE4 instructions that will appear in its next-generation 45nm products. The new SSE4 instructions add 50 new performance enhancing instructions. These instructions optimize vector compiling, media, string and text processing and application targeted accelerators.

The Core architecture implemented on the Core 2 Duo processors added 32 additional supplimental streaming instructions to SSE3.  These instructions, dubbed Supplimental Streaming SIMD, are not SSE4 and should not be confused as such.

SSE4 instructions are expected to arrive incrementally in Intel’s first 45nm product that is expected to sample in the second half of 2007. This includes Intel’s upcoming Nehalem, which will be Intel’s second generation Core architecture, and Penryn, a 45nm shrink of Core 2 Duo. Intel Penryn and other 45nm processors are expected to begin sampling the second half of 2007 and begin shipping in the first half of 2008.  Full implementation of SSE4 is only planned for Nehalem at this time.

More details are available in Intel's whitepaper on the subject.



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RE: Core?
By hstewarth on 9/27/2006 6:09:03 PM , Rating: 2
Or maybe its more simple than that - a simple software switch. Once software is available, it can be just turn on. I thought Core 2 had these instruction set.


RE: Core?
By Kougar on 9/27/2006 7:03:56 PM , Rating: 2
Core 2 Duo has the SSE4 instruction set. Which is probably why Penryn, the die shrink of Conroe, is reported by Cnet to have them.


RE: Core?
By KristopherKubicki (blog) on 9/27/2006 7:18:17 PM , Rating: 3
Core 2 Duo has 32 new instructions from SSE3, dubbed Sipplimental Streaming SIMD. These are *not* the instruction set dubbed SSE4. SSE4 are 50 new instructions and will show up in 2008 at the earliest.

CNET reported this as Penryn because that is when the first 45nm node chips. Nehalem is the next generation architecture after Penryn, and will also use the SSE4 instructions


RE: Core?
By Kougar on 9/28/2006 3:58:39 AM , Rating: 2
Okay, so basically a SSE3.1, or something to that effect? That makes better sense to me, thanks.

SSE4 was being touted around during the C2D launch, infact some stores list all C2D's as having SSE4 on them. Which is sort of ironic because I can't find any documentation now when I was looking for it.


RE: Core?
By FITCamaro on 9/28/2006 12:53:12 PM , Rating: 2
Not to mention CPU-Z reports my E6600 as having SSE4.


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