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Print 30 comment(s) - last by saratoga.. on Nov 14 at 8:32 PM


A quick list of new SSE instructions - Image courtesy HotHardware
Fourth generation streaming SIMD extensions

With Intel’s Conroe Core 2 Duo launch in June 2006, Intel added several new SSE optimizations. The new SSE optimizations included with Intel’s Core 2 architecture sped up SSE, SSE2 and SSE3 operations two-fold. This was performed by optimizing the Core 2 architecture to execute a 128-bit SSE, SSE2 and SSE3 instruction in a single clock cycle. Intel’s previous Netburst and Core architecture required two clock cycles to execute the same instruction. These extensions and optimizations of SSE3 were not actually new instructions but more or less an improvement in efficiency.

Intel’s Pat Gelsinger announced today that Intel has published the white paper on its SSE4 instructions that will appear in its next-generation 45nm products. The new SSE4 instructions add 50 new performance enhancing instructions. These instructions optimize vector compiling, media, string and text processing and application targeted accelerators.

The Core architecture implemented on the Core 2 Duo processors added 32 additional supplimental streaming instructions to SSE3.  These instructions, dubbed Supplimental Streaming SIMD, are not SSE4 and should not be confused as such.

SSE4 instructions are expected to arrive incrementally in Intel’s first 45nm product that is expected to sample in the second half of 2007. This includes Intel’s upcoming Nehalem, which will be Intel’s second generation Core architecture, and Penryn, a 45nm shrink of Core 2 Duo. Intel Penryn and other 45nm processors are expected to begin sampling the second half of 2007 and begin shipping in the first half of 2008.  Full implementation of SSE4 is only planned for Nehalem at this time.

More details are available in Intel's whitepaper on the subject.



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The Wisdom of new instruction set
By knitecrow on 9/27/2006 5:40:00 PM , Rating: 0
I don't question the potential advantage (even if it is minuscule) offered by the new instructions but the logic of releasing new instruction sets when people don't even support the old ones.

Only now are we seeing wide support for SSE2; SSE3 support is minimal at best. Does the industry need SSE4?

Why not work with others in the industry (like AMD) and release instructions that software developers are asking for and will pledge support for.




RE: The Wisdom of new instruction set
By hstewarth on 9/27/06, Rating: 0
By saratoga on 11/14/2006 8:32:27 PM , Rating: 2
quote:
Because Intel has the right to enhanced there own instruction set which they designed. AMD did not designed the x86 processor that we have today and Intel does not need confirm its designed with AMD.


Actually, AMD (as well as MS to a lesser extent) is largely behind the recent move to SSE2 because they force you to use it in their x86-64 extension. Although Intel came up with (most) of SSE2, the final implementation was actually from AMD (which tweaked it with new registers), with Intel quietly adopting it when MS forced then to support x86-64


RE: The Wisdom of new instruction set
By DallasTexas on 9/27/06, Rating: -1
RE: The Wisdom of new instruction set
By ergle on 9/27/2006 7:43:31 PM , Rating: 2
I was with you 'til the Intel fanboi-ism kicked in.

AMD generally adopts new instruction sets quickly and 3DNow had widespread support at the time, especially in games and drivers.

3DNow includes a subset of the original SSE.


RE: The Wisdom of new instruction set
By tygrus on 9/27/2006 11:30:31 PM , Rating: 2
quote:
3DNow includes a subset of the original SSE.


Actually, I think it was the other way around. AMD introduced 3DNow before Intel had SSE. Some of 3DNow instructions were same as Intel SSE but the context/mode switch was different. AMD further added to 3DNow before continuing with SSE# after license fight and for simplicity.
The AMD K6-2 & K6-3 chips were good for most but had a limited future due to limited scailing, slow x87 FPU, and newer PIII, P4 and K7. 3DNow overcame some of the slow x87 FPU problems and made it competative against PII and early PIII.


RE: The Wisdom of new instruction set
By ergle on 9/28/2006 2:04:03 AM , Rating: 2
Yeah, 3DNow was first, but it still only contains a subset of SSE.

My comments weren't meant to confer that the K6 was wonderful. As someone who's worked with both, I'm well aware of the K6's shortcomings -- especially the lack of a pipelined FPU.

I do find it rather odd I was troll-rated for calling someone on their trolling tho'. Not your doing, I know :)


By kobymu on 9/28/2006 6:53:30 AM , Rating: 3
quote:
yeah, 3DNow was first, but it still only contains a subset of SSE.


MMX was first , and was extremely successful, which is the only reason why AMD created 3DNew in the first place.

quote:
Why not work with others in the industry (like AMD) and release instructions that software developers are asking for and will pledge support for.


"pledge support" ??? ...anyway, MMX was a huge success because Intel did just that, they listen to programmers and clients how wanted multimedia enhancements.

And not only was MMX a huge success, it was a fast success; programmers adopted MMX in almost unprecedented speed, unlike 486 new instructions or Pentium new instructions or even Pentium pro newer instructions, which most programmers took literally years to adopt.

IIRC Photoshop was the first 'big' adopter; only a few months after MMX initial release (don't remember the exact version though).


By smitty3268 on 9/27/2006 11:18:50 PM , Rating: 2
quote:
As far as AMD is concerned, yes, they adopt Intel extentions about 10 years later. They also come out with some of their own like 3DNow which found it's way into one Disney applications - I think it was Goofy.


More like 1 year later. Anyway, 3Dnow (and its successors) were actually quite popular with games and other apps early on. They were pretty much eclipsed by SSE/2 though.


"We are going to continue to work with them to make sure they understand the reality of the Internet.  A lot of these people don't have Ph.Ds, and they don't have a degree in computer science." -- RIM co-CEO Michael Lazaridis

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