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Paul Otellini holds up a wafer with 6400 cores
Intel promises teraflop chips within the next five years

Intel today announced that it has produced its first teraflop-on-a-chip.  The chip, essentially a prototype, was demonstrated when Intel CEO Paul Otellini showed off the wafer during this week's IDF conference opening keynote.

Each of the 80 processors on the wafer contain a die with eighty cores -- 6400 cores in total.  Each CPU has more than one terabyte per second of throughput between the CPU cores and the on-die SRAM. Otellini claims that this technology will be available within 5 years, putting it in line with the previously outlined Gesher family expected to ship in 2010. 

To put that into perspective, the fastest public supercomputer in 1996 was the ASCI Red which featured over 4,500 compute nodes using 200MHz Pentium Pro processors and was the first computer to break the 1 teraflops barrier.

Each of the individual CPUs runs at 3.1GHz in a very simple configuration.  These are far from production-ready processors and are mainly for demonstration purposes.  Each processor is also unique in the fact that the packaging is three dimensional.  The cache substrate is "stacked" directly underneath the FPUs, thus saving space and latency. 

The processors are just one component of Intel's Tera-Scale initiative -- a set of research projects geared to bringing multi-teraflop systems to the masses by 2010.  More objectives of this project, including software design, will be announced later during the Intel Developer Forum.

Intel also today announced the official name for its quad-core desktop and server CPU: the Core 2 Quad. As its name implies, the processor contains four cores and features a 1066MHz front-side bus. For benchmarks on the Core 2 Quad, you can check out DailyTech’s Kentsfield article from yesterday.



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By psychobriggsy on 9/27/2006 11:53:18 AM , Rating: 2
This is a similar development to Cell, however it is 4 or 5 years off. Certainly it seems a reaction to Cell, rather than a reaction to dual/quad x86 cores. It'll probably be used for graphics and physics processing in a system instead of a GPU.

Cell has 8 dual-pipelined SIMD cores (alongside the PowerPC core) and gets 1/4 of the speed of this Intel design. That suggests that the Intel core is single pipelined SIMD, or quad-pipeline single-precision. 80 * 3.1GHz * 4 = 992GFLOPS, near enough 1TFLOP.

Give Cell a process shrink to 65nm, and you can fit on 16 SPUs on a chip, running at 4GHz, for 16 * 4GHz * 8 = 512GFLOPS. However Intel's inter-core technology will probably scale better than Cell's ring topology.

Intel should stick a HyperTransport interface on this chip and sell it for use with AMD's Torrenza technology, it seems like an ideal match! :)

Needless to say the future of CPUs and GPUs is interesting again.




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