Print 51 comment(s) - last by Tyler 86.. on Oct 3 at 1:16 PM

Paul Otellini holds up a wafer with 6400 cores
Intel promises teraflop chips within the next five years

Intel today announced that it has produced its first teraflop-on-a-chip.  The chip, essentially a prototype, was demonstrated when Intel CEO Paul Otellini showed off the wafer during this week's IDF conference opening keynote.

Each of the 80 processors on the wafer contain a die with eighty cores -- 6400 cores in total.  Each CPU has more than one terabyte per second of throughput between the CPU cores and the on-die SRAM. Otellini claims that this technology will be available within 5 years, putting it in line with the previously outlined Gesher family expected to ship in 2010. 

To put that into perspective, the fastest public supercomputer in 1996 was the ASCI Red which featured over 4,500 compute nodes using 200MHz Pentium Pro processors and was the first computer to break the 1 teraflops barrier.

Each of the individual CPUs runs at 3.1GHz in a very simple configuration.  These are far from production-ready processors and are mainly for demonstration purposes.  Each processor is also unique in the fact that the packaging is three dimensional.  The cache substrate is "stacked" directly underneath the FPUs, thus saving space and latency. 

The processors are just one component of Intel's Tera-Scale initiative -- a set of research projects geared to bringing multi-teraflop systems to the masses by 2010.  More objectives of this project, including software design, will be announced later during the Intel Developer Forum.

Intel also today announced the official name for its quad-core desktop and server CPU: the Core 2 Quad. As its name implies, the processor contains four cores and features a 1066MHz front-side bus. For benchmarks on the Core 2 Quad, you can check out DailyTech’s Kentsfield article from yesterday.

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RE: Ok....
By UNHchabo on 9/27/2006 10:50:17 AM , Rating: 2
Maybe that's when they added L2 cache, but I was pretty sure that processors have had cache of some sort for considerably longer than that.

RE: Ok....
By defter on 9/27/2006 12:29:32 PM , Rating: 2
No, 486 was when they added L1 cache. L2 cache was added in 1998 with Celeron-A. Before 486, Intel didn't have any cache within x86 CPUs.

RE: Ok....
By codeThug on 9/29/2006 10:39:11 PM , Rating: 2
They did. They call them REGISTERS.

RE: Ok....
By Tyler 86 on 10/1/2006 1:28:40 AM , Rating: 2
Eh.. Technicly, registers are not cache, since they're directly accessible...
Cache is indirectly accessible by accessing prefetched or previously accessed memory locations...

mov al, 0x4000
inc al

then al no longer equals 0x4000,

whereas, with cache...

you could technicly somehow directly set the cache line for 0x4000 w/o accessing memory, possibly by an out-of-order instruction optimization, eg;
mov bl, 0x4000
mov 0x4000, al
bl -> cached 0x4000 -> al -> 0x4000
but more optimized would be
bl -> al -> 0x4000

... but no intelligent compiler would create such a circumstance... so...

... registers aren't cache...

RE: Ok....
By Tyler 86 on 10/1/2006 1:29:19 AM , Rating: 2
nowadays, there's a couple of kB worth of L1 cache that aren't registers...

"Nowadays you can buy a CPU cheaper than the CPU fan." -- Unnamed AMD executive
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