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64-bit Celeron to debut in Q1 of next year, with rumours of dual-core abound

DailyTech has received roadmaps outlining Intel’s value mobile plans. Intel is preparing to launch a pair of low-cost Celeron processors based on the current Core 2 Duo Merom architecture. The new Celeron processors will not bear Intel's Core nomenclature.  These new processors are scheduled to launch in Q1'07.

Intel Merom Celeron M Plans
Processor
Number
Core
Frequency
Bus
Frequency
L2
Cache
530 1.73GHz 533MHz 1MB
520 1.60GHz 533MHz 1MB

Instead of the new Core 2 Duo moniker, these Merom derivatives will be known as the Celeron M 500 series. Two models will be available initially: the Celeron M 520 and 530. These processors will be clocked at 1.60 and 1.73GHz respectively. Both will have 1MB of shared L2 cache and run on a 533MHz FSB. Intel's EMT64 and XD extensions are also supported. Manufacturing will be done on a 65nm process.

Despite previous speculation by DigiTimes, the new Merom based Celeron M 500 series will not be dual-core. DailyTech has confirmed with various Taiwanese manufacturers regarding the matter. Although the Celeron M 500 series are based on Intel’s Merom core, one processor core will be disabled on Celeron variants.

Pricing for the Celeron M 520 will be $134 in 1,000-unit lots.  Pricing for the M 530 has not yet been released.


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RE: Shared chache ?
By PrinceGaz on 9/21/2006 9:58:14 PM , Rating: 2
Strictly speaking it is shared L2 cache. The fact that what it is shared with is a disabled second core which therefore will never use (or only have a token minimum amount reserved for it) it doesn't change the fact that it is shared.

Calling it a shared L2 cache when there is only one functional core using it does seem a bit silly really though.


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