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The first native x86 quad-core processor is finally taped out

With the news of AMD's DDR2 Opteron launch, AMD managed to squeeze in one tidbit of information definitely newsworthy: quad-core Opterons have been taped out. AMD's Executive Vice President Henri Richard had previously dubbed these native quad-core design as the K8L architecture.  Internally at AMD, this architecture is known as Greyhound.

The company's press release claims "AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon." For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.

The press release further adds that the quad-core Opteron will be compatible with the dual-core DDR2 Opteron motherboards.  The news of backwards compatibility with existing DDR2 Opteron motherboards is in line with AMD's previous announcements on its other platforms.  On roadmaps earlier this year the company also claimed that AM3 processors would be compatible with AM2 motherboards.

Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year.  Intel's initial quad-core designs are significantly different than AMD's approach.  The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package.  AMD's native quad-core, on the other hand, incorporates all four cores onto the same die.  AMD countered Intel's accelerated roadmap by claiming the new quad-core processors would be demonstrated this year.

However, absent from AMD's quad-core announcement is any news of non-native quad-core processors.  Non-native quad-core Opterons, previously dubbed Deerhound, existed on AMD's roadmap as late as May of this year.  These 65nm processors were essentially two 65nm dual-core Opterons on the same package, but AMD has made virtually no comment on any 65nm dual or single-core processors since the AMD Analyst Day on June 1 of this year.  AMD still plans to introduce 65nm dual-core processors for desktops this year.

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RE: What exactly is Tape Out
By kilkennycat on 8/15/2006 9:23:47 PM , Rating: 3
The digital data tapes used to create the master patterns for the silicon and conductor layers on the silicon wafers from which the individual chips are cut after probe-testing. Tape out means that the chip-design is complete for the target process ( presumably 65nm in this case ). Following first tape-out, masks are made and prototype wafers are run. With in-house mask-creation facilities, these two steps usually take 8-10 weeks. Can be shorter, but I'm sure that a lot of careful double-checking will go into a first run of a new part on a new process. After the wafers are run and probe-tested, the real hard work of checking out all of the logic and electrical functionality begins. Typically a new CPU needs several design/mask/fab/exhaustive-test/ cycles before it can be shipped. And some of these design changes are likely to include tweaks to improve process yields, as well as correcting logic problems. Hence, the estimate for the quad-core being customer-available mid-07 is not far off the mark.

RE: What exactly is Tape Out
By Questar on 8/15/2006 10:57:40 PM , Rating: 2
And some of these design changes are likely to include tweaks to improve process yields

You've got it correct except for that line. It would be insane to make design changes at this point to attempt to increase yeild. Design to process rules are already complete long, long before a chip makes it to tape out. It would be a major bungle to have to respin a chip due to missing yeild targets, and hugely costly. Hell, the delay could be a year.

RE: What exactly is Tape Out
By kilkennycat on 8/16/2006 1:49:33 PM , Rating: 2
The design tweaks to improve chip-yields are mostly related to tweaking logic to improve timing margins. Other tweaks are also applied to optimize power-consumption. Device and timing modeling for a new process is not initially as accurate as for a mature process; models continue to be honed as the process matures. Thus the tweaks in each mask-set update are usually a combination of logic fixes and yield/power-consumption optimizations.

RE: What exactly is Tape Out
By Phynaz on 8/16/2006 4:00:17 PM , Rating: 2
Device and timing modeling for a new process is not initially as accurate as for a mature process

Which is why no sane person (or company) would link a new chip design to a new manufacturing process.

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