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The first native x86 quad-core processor is finally taped out

With the news of AMD's DDR2 Opteron launch, AMD managed to squeeze in one tidbit of information definitely newsworthy: quad-core Opterons have been taped out. AMD's Executive Vice President Henri Richard had previously dubbed these native quad-core design as the K8L architecture.  Internally at AMD, this architecture is known as Greyhound.

The company's press release claims "AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon." For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.

The press release further adds that the quad-core Opteron will be compatible with the dual-core DDR2 Opteron motherboards.  The news of backwards compatibility with existing DDR2 Opteron motherboards is in line with AMD's previous announcements on its other platforms.  On roadmaps earlier this year the company also claimed that AM3 processors would be compatible with AM2 motherboards.

Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year.  Intel's initial quad-core designs are significantly different than AMD's approach.  The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package.  AMD's native quad-core, on the other hand, incorporates all four cores onto the same die.  AMD countered Intel's accelerated roadmap by claiming the new quad-core processors would be demonstrated this year.

However, absent from AMD's quad-core announcement is any news of non-native quad-core processors.  Non-native quad-core Opterons, previously dubbed Deerhound, existed on AMD's roadmap as late as May of this year.  These 65nm processors were essentially two 65nm dual-core Opterons on the same package, but AMD has made virtually no comment on any 65nm dual or single-core processors since the AMD Analyst Day on June 1 of this year.  AMD still plans to introduce 65nm dual-core processors for desktops this year.

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RE: So.......
By TomZ on 8/15/2006 5:25:20 PM , Rating: 2
Well, in this case, I would think the 4 cores can exchange data via the crossbar switch instead of doing it via RAM.

Why are you guys so interested in CPU-to-CPU data transfers? I would think that nearly all computing scenarios would not have much of that type of transfer. Actually, I have a hard time thinking of any such application. What would be an example of one?

RE: So.......
By ZachSaw on 8/16/2006 3:55:58 AM , Rating: 2
Inter-CPU cache syncs via MESI protocol.

This is a rather significant overhead for multi-cpu configs. Kentfield will have this problem, but it won't be apparent (thanks to its low mem bandwidth usage). But if you have 2 Kentfields running, it'll be a different story.

RE: So.......
By TomZ on 8/16/2006 9:00:10 PM , Rating: 2
Inter-CPU cache syncs via MESI protocol.

What sorts of applications would require inter-CPU cache syncs?

RE: So.......
By ZachSaw on 8/17/2006 3:46:41 AM , Rating: 2
Anything that uses more than one processor... DUH!

RE: So.......
By TomZ on 8/17/06, Rating: 0
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