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The first native x86 quad-core processor is finally taped out

With the news of AMD's DDR2 Opteron launch, AMD managed to squeeze in one tidbit of information definitely newsworthy: quad-core Opterons have been taped out. AMD's Executive Vice President Henri Richard had previously dubbed these native quad-core design as the K8L architecture.  Internally at AMD, this architecture is known as Greyhound.

The company's press release claims "AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon." For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.

The press release further adds that the quad-core Opteron will be compatible with the dual-core DDR2 Opteron motherboards.  The news of backwards compatibility with existing DDR2 Opteron motherboards is in line with AMD's previous announcements on its other platforms.  On roadmaps earlier this year the company also claimed that AM3 processors would be compatible with AM2 motherboards.

Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year.  Intel's initial quad-core designs are significantly different than AMD's approach.  The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package.  AMD's native quad-core, on the other hand, incorporates all four cores onto the same die.  AMD countered Intel's accelerated roadmap by claiming the new quad-core processors would be demonstrated this year.

However, absent from AMD's quad-core announcement is any news of non-native quad-core processors.  Non-native quad-core Opterons, previously dubbed Deerhound, existed on AMD's roadmap as late as May of this year.  These 65nm processors were essentially two 65nm dual-core Opterons on the same package, but AMD has made virtually no comment on any 65nm dual or single-core processors since the AMD Analyst Day on June 1 of this year.  AMD still plans to introduce 65nm dual-core processors for desktops this year.


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RE: So.......
By defter on 8/15/2006 1:00:28 PM , Rating: 2
quote:
this means that the cores communicate through the L2 cache crossbar instead of the FSB


However, AMD's "native quad-core design" won't have shared L2 cache...

The term "native" shouldn't overused or overhyped simply because there are so many ways to define it. For example is native quad/dual-core design which has:
- shared L1 cache (AFAIK none of these kind of designs exists)?
- separate L1 but shared L2 cache (Yonah/Merom)?
- separate L1 and L2 caches but shared L3 cache (Tulsa/new Itanium/K8L)?
- separate caches but shared interface to the memory/IO (K8)?
- separate caches and interfaces to the memory/IO but a single die (Smithfield)?

As you can see, "native" quad/dual-core can mean many things.


RE: So.......
By psychobriggsy on 8/15/2006 1:44:22 PM , Rating: 2
Smithfield was two dies, in a single package.

Otherwise, when restricting the definition to single-die chips, it's merely a matter of choosing where to put the arbiter that interfaces the multiple cores + their individual caches to the shared resources (lower level caches and interface to FSB/integrated northbridge.

"Native" in AMD's case means 'single die that has multiple cores, but externally appears to have the same I/O as a single die should'.

As an aside: Indeed you could even stretch that to include multiple dies, as long as the CPU package appears to the system as a single processor, not multiple bus loads on a FSB, i.e., to any system these are used as replacements they will work as expected, losing nothing. That's why I wondered why AMD didn't do multi-die consumer processors using HyperTransport on the package to communicate between dies. I guess that Multi-Chip-Modules aren't AMD's forté.


RE: So.......
By defter on 8/15/2006 3:32:09 PM , Rating: 2
quote:
Smithfield was two dies, in a single package.


No, Smithfield is a single die design: http://www.at-mix.de/images/news/0014-intel-smithf...



RE: So.......
By PT2006 on 8/15/2006 6:20:33 PM , Rating: 2
Smithfield is a single die. Presler is basically two Cedar Mills slapped together though.


RE: So.......
By Viditor on 8/15/2006 8:09:54 PM , Rating: 2
quote:
Smithfield is a single die. Presler is basically two Cedar Mills slapped together though


No, both Smithfield and Presler are 2 dies glued together (known as MCMs), and they require the FSB to negotiate cache coherency.


RE: So.......
By coldpower27 on 8/16/2006 12:57:33 AM , Rating: 2

Smithfield is a single die, unlike Presler which is 2 dice.

However Smithfield is something like 2 Prescotts side by side, since it is a Single Dice.

Presler has the advantage of being any 2 dice, on a wafer and since they don't come from side by side necessarily, they are sperate dice.

Hence why the die size is 2x81mm2 for Presler but 206mm2 for Smithfield.


RE: So.......
By Viditor on 8/15/2006 8:13:48 PM , Rating: 2
quote:
That's why I wondered why AMD didn't do multi-die consumer processors using HyperTransport on the package to communicate between dies


Speed...HT isn't nearly as fast as the crossbar used in both the native dual core or the upcoming native quad core (and neither is Intel's MCMs).


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