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The first native x86 quad-core processor is finally taped out

With the news of AMD's DDR2 Opteron launch, AMD managed to squeeze in one tidbit of information definitely newsworthy: quad-core Opterons have been taped out. AMD's Executive Vice President Henri Richard had previously dubbed these native quad-core design as the K8L architecture.  Internally at AMD, this architecture is known as Greyhound.

The company's press release claims "AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon." For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.

The press release further adds that the quad-core Opteron will be compatible with the dual-core DDR2 Opteron motherboards.  The news of backwards compatibility with existing DDR2 Opteron motherboards is in line with AMD's previous announcements on its other platforms.  On roadmaps earlier this year the company also claimed that AM3 processors would be compatible with AM2 motherboards.

Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year.  Intel's initial quad-core designs are significantly different than AMD's approach.  The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package.  AMD's native quad-core, on the other hand, incorporates all four cores onto the same die.  AMD countered Intel's accelerated roadmap by claiming the new quad-core processors would be demonstrated this year.

However, absent from AMD's quad-core announcement is any news of non-native quad-core processors.  Non-native quad-core Opterons, previously dubbed Deerhound, existed on AMD's roadmap as late as May of this year.  These 65nm processors were essentially two 65nm dual-core Opterons on the same package, but AMD has made virtually no comment on any 65nm dual or single-core processors since the AMD Analyst Day on June 1 of this year.  AMD still plans to introduce 65nm dual-core processors for desktops this year.

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RE: So.......
By icarus4586 on 8/15/2006 8:34:15 AM , Rating: 2
With "non-native" (if that's what they're calling it now) multicore solutions, data does not have to go core->fsb->ram->fsb->other core. It doesn't even have to go to the northbridge. Just core->fsb->other core. The way you described would have absurdly high latency.

RE: So.......
By Griswold on 8/15/2006 10:27:50 AM , Rating: 2
Ok. But that would depend on how many FSB channels there are per socket. Is it just one for both packages or 2 channels, one for each package? If it's the latter, I fail to see how it would work without at least doing the NB hop.

RE: So.......
By Flunk on 8/15/2006 2:49:25 PM , Rating: 2
Yes, I'm reasonably certain they have to go CPU1->Northbridge->CPU2 and vice versa.

Except for AMD designs where depending on the number of hypertransport links even non-native multicore processors can connect directly to each other assumeing there are enough HT links on the cores (for a non-native quad core composed of two native dual cores they would each need 2 HT links. One to the northbridge and on to the other on-chip processor die.).

RE: So.......
By ZachSaw on 8/16/06, Rating: 0
RE: So.......
By JeffDM on 8/17/2006 12:22:26 PM , Rating: 2
The Kentsfield will share an FSB internally, it's not like two separate busses within the processor socket. However, I don't know if the Intel CPUs would share data like that.

With AMD's arrangement, it looks like they will simply share cache, I don't think cores would directly communicate to each other with HyperTransport unless you have a two-socket system.

Missing is that the generation after Kentsfield will be a shared die, shared cache setup, last I heard, it was set for about mid-2007.

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