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The first native x86 quad-core processor is finally taped out

With the news of AMD's DDR2 Opteron launch, AMD managed to squeeze in one tidbit of information definitely newsworthy: quad-core Opterons have been taped out. AMD's Executive Vice President Henri Richard had previously dubbed these native quad-core design as the K8L architecture.  Internally at AMD, this architecture is known as Greyhound.

The company's press release claims "AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon." For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.

The press release further adds that the quad-core Opteron will be compatible with the dual-core DDR2 Opteron motherboards.  The news of backwards compatibility with existing DDR2 Opteron motherboards is in line with AMD's previous announcements on its other platforms.  On roadmaps earlier this year the company also claimed that AM3 processors would be compatible with AM2 motherboards.

Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year.  Intel's initial quad-core designs are significantly different than AMD's approach.  The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package.  AMD's native quad-core, on the other hand, incorporates all four cores onto the same die.  AMD countered Intel's accelerated roadmap by claiming the new quad-core processors would be demonstrated this year.

However, absent from AMD's quad-core announcement is any news of non-native quad-core processors.  Non-native quad-core Opterons, previously dubbed Deerhound, existed on AMD's roadmap as late as May of this year.  These 65nm processors were essentially two 65nm dual-core Opterons on the same package, but AMD has made virtually no comment on any 65nm dual or single-core processors since the AMD Analyst Day on June 1 of this year.  AMD still plans to introduce 65nm dual-core processors for desktops this year.


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To quote Ron Burgundy
By BaronMatrix on 8/15/2006 7:56:37 AM , Rating: 2
Yaaayyyy!




So.......
By qdemn7 on 8/15/2006 8:02:14 AM , Rating: 2
So what are the advantages / disadvantages of native vs non-native quad cores?


RE: So.......
By Griswold on 8/15/2006 8:09:54 AM , Rating: 1
Well, in this case, I would think the 4 cores can exchange data via the crossbar switch instead of doing it via RAM.

On Intels side, theres shared cache for 2 cores alright, but if the 2 packages want to share data, it'll crawl over the FSB to RAM and back to the other package via FSB instead.


RE: So.......
By icarus4586 on 8/15/2006 8:34:15 AM , Rating: 2
With "non-native" (if that's what they're calling it now) multicore solutions, data does not have to go core->fsb->ram->fsb->other core. It doesn't even have to go to the northbridge. Just core->fsb->other core. The way you described would have absurdly high latency.


RE: So.......
By Griswold on 8/15/2006 10:27:50 AM , Rating: 2
Ok. But that would depend on how many FSB channels there are per socket. Is it just one for both packages or 2 channels, one for each package? If it's the latter, I fail to see how it would work without at least doing the NB hop.



RE: So.......
By Flunk on 8/15/2006 2:49:25 PM , Rating: 2
Yes, I'm reasonably certain they have to go CPU1->Northbridge->CPU2 and vice versa.

Except for AMD designs where depending on the number of hypertransport links even non-native multicore processors can connect directly to each other assumeing there are enough HT links on the cores (for a non-native quad core composed of two native dual cores they would each need 2 HT links. One to the northbridge and on to the other on-chip processor die.).


RE: So.......
By ZachSaw on 8/16/06, Rating: 0
RE: So.......
By JeffDM on 8/17/2006 12:22:26 PM , Rating: 2
The Kentsfield will share an FSB internally, it's not like two separate busses within the processor socket. However, I don't know if the Intel CPUs would share data like that.

With AMD's arrangement, it looks like they will simply share cache, I don't think cores would directly communicate to each other with HyperTransport unless you have a two-socket system.

Missing is that the generation after Kentsfield will be a shared die, shared cache setup, last I heard, it was set for about mid-2007.


RE: So.......
By TomZ on 8/15/2006 5:25:20 PM , Rating: 2
quote:
Well, in this case, I would think the 4 cores can exchange data via the crossbar switch instead of doing it via RAM.

Why are you guys so interested in CPU-to-CPU data transfers? I would think that nearly all computing scenarios would not have much of that type of transfer. Actually, I have a hard time thinking of any such application. What would be an example of one?


RE: So.......
By ZachSaw on 8/16/2006 3:55:58 AM , Rating: 2
Inter-CPU cache syncs via MESI protocol.

This is a rather significant overhead for multi-cpu configs. Kentfield will have this problem, but it won't be apparent (thanks to its low mem bandwidth usage). But if you have 2 Kentfields running, it'll be a different story.


RE: So.......
By TomZ on 8/16/2006 9:00:10 PM , Rating: 2
quote:
Inter-CPU cache syncs via MESI protocol.

What sorts of applications would require inter-CPU cache syncs?


RE: So.......
By ZachSaw on 8/17/2006 3:46:41 AM , Rating: 2
Anything that uses more than one processor... DUH!


RE: So.......
By TomZ on 8/17/06, Rating: 0
RE: So.......
By icarus4586 on 8/15/2006 8:31:32 AM , Rating: 2
Native is a silly thing to call it, in my opinion. My guess is that, just as Griswold said, this means that the cores communicate through the L2 cache crossbar instead of the FSB. So, practically speaking, you'll get a little bit bigger relative advantage between 2 and 4 cores than you would with Intel. Probably a couple percents.


RE: So.......
By KristopherKubicki (blog) on 8/15/2006 8:43:29 AM , Rating: 2
I am fairly certain I read somewhere that Kentsfield allows the two cores to communicate directly on the chip package and not over the FSB. I will try to dig that up.

The "real" difference between a native and a non-native design is that in a native design it's a single die while a non-native design would be multiple dies. Whether or not this actually maeks a difference to performance is something else entirely.


RE: So.......
By The Boston Dangler on 8/15/2006 9:03:28 AM , Rating: 3
Shouldn't prices be lower on non-native parts? The use of 2 dice increases yields, for a small manufacturing hit.


RE: So.......
By Furen on 8/15/2006 9:45:26 AM , Rating: 2
They should but they likely won't. I'm guessing it'll just have higher profit margins for Intel.


RE: So.......
By TomZ on 8/15/2006 5:27:01 PM , Rating: 2
Yes, prices are determined based on market demand and value of the product, not just on manufacturing cost.


RE: So.......
By ElFenix on 8/16/2006 12:27:21 AM , Rating: 2
intel had a dual dice package that was tremendously expensive. it was the pentium pro. if just one die was broken (either the core or the SRAM) both had to be tossed out. that is the reason intel moved to putting processors on daughtercards with a backside cache on the daughtercard. eventually manufacturing caught up to design and both could be integrated into a single die.

of course, two dice like that might be less expensive than trying to make one massive die. intel must have thought so to begin with.


RE: So.......
By Viditor on 8/15/2006 10:36:01 AM , Rating: 2
quote:
I am fairly certain I read somewhere that Kentsfield allows the two cores to communicate directly on the chip package and not over the FSB. I will try to dig that up


Interesting...please do! I wonder what protocol they would use and how the signals will be sent/received?


RE: So.......
By KristopherKubicki (blog) on 8/19/2006 10:27:21 AM , Rating: 2
Check out ZackSaw's post a little bit above this one.


RE: So.......
By defter on 8/15/2006 1:00:28 PM , Rating: 2
quote:
this means that the cores communicate through the L2 cache crossbar instead of the FSB


However, AMD's "native quad-core design" won't have shared L2 cache...

The term "native" shouldn't overused or overhyped simply because there are so many ways to define it. For example is native quad/dual-core design which has:
- shared L1 cache (AFAIK none of these kind of designs exists)?
- separate L1 but shared L2 cache (Yonah/Merom)?
- separate L1 and L2 caches but shared L3 cache (Tulsa/new Itanium/K8L)?
- separate caches but shared interface to the memory/IO (K8)?
- separate caches and interfaces to the memory/IO but a single die (Smithfield)?

As you can see, "native" quad/dual-core can mean many things.


RE: So.......
By psychobriggsy on 8/15/2006 1:44:22 PM , Rating: 2
Smithfield was two dies, in a single package.

Otherwise, when restricting the definition to single-die chips, it's merely a matter of choosing where to put the arbiter that interfaces the multiple cores + their individual caches to the shared resources (lower level caches and interface to FSB/integrated northbridge.

"Native" in AMD's case means 'single die that has multiple cores, but externally appears to have the same I/O as a single die should'.

As an aside: Indeed you could even stretch that to include multiple dies, as long as the CPU package appears to the system as a single processor, not multiple bus loads on a FSB, i.e., to any system these are used as replacements they will work as expected, losing nothing. That's why I wondered why AMD didn't do multi-die consumer processors using HyperTransport on the package to communicate between dies. I guess that Multi-Chip-Modules aren't AMD's forté.


RE: So.......
By defter on 8/15/2006 3:32:09 PM , Rating: 2
quote:
Smithfield was two dies, in a single package.


No, Smithfield is a single die design: http://www.at-mix.de/images/news/0014-intel-smithf...



RE: So.......
By PT2006 on 8/15/2006 6:20:33 PM , Rating: 2
Smithfield is a single die. Presler is basically two Cedar Mills slapped together though.


RE: So.......
By Viditor on 8/15/2006 8:09:54 PM , Rating: 2
quote:
Smithfield is a single die. Presler is basically two Cedar Mills slapped together though


No, both Smithfield and Presler are 2 dies glued together (known as MCMs), and they require the FSB to negotiate cache coherency.


RE: So.......
By coldpower27 on 8/16/2006 12:57:33 AM , Rating: 2

Smithfield is a single die, unlike Presler which is 2 dice.

However Smithfield is something like 2 Prescotts side by side, since it is a Single Dice.

Presler has the advantage of being any 2 dice, on a wafer and since they don't come from side by side necessarily, they are sperate dice.

Hence why the die size is 2x81mm2 for Presler but 206mm2 for Smithfield.


RE: So.......
By Viditor on 8/15/2006 8:13:48 PM , Rating: 2
quote:
That's why I wondered why AMD didn't do multi-die consumer processors using HyperTransport on the package to communicate between dies


Speed...HT isn't nearly as fast as the crossbar used in both the native dual core or the upcoming native quad core (and neither is Intel's MCMs).


RE: So.......
By raddude9 on 8/16/2006 5:07:37 AM , Rating: 2
Shared cache is one of the advantages.
One of the advantages that Conroe has over the current AMD chips is that more cache can be given to the CPU that needs it more, unlike the dual-core AMDs where the cache is exclusive to the core. The dual core AMD's get abour this somewhat by having a HT link between the cores, unlike the nasty old pentium D's where the two cores had to talk off-chip as it were.


RE: To quote Ron Burgundy
By Comdrpopnfresh on 8/23/2006 9:35:04 PM , Rating: 2
I see great things for this chip. Perhaps something like RHT (even though it is supposedly a myth...). With it coming out at the time of vista on the market, four cores, and HT-interconnects between the cores and the chip to the system... With the native x64 support, and an x64 OS to support it I think this chip's biggest asset, especially because of it being an Operton (maybe with any athlon-like quads too), is that it will be able to handle up to terabytes of memory. Maybe we won't start there, but imagine 16 gigs of say, DDR3, or XDR? Imagine the possibilites! Unless you had to save a document, everything would be contained on the ram, and within the L-cache. This type of technology cannot be met by Intel; because, in order to have communications between the cores and the ram too, the FSB wuld be split way too thinly, but with an onboard memory contorller like AMD has, they can go right ot native. Conroe as it is (w/o a mem controller) will perform horribly if put in a native-quad, and even the dual-dual they are coming out with. There simply isn't enough bandwidth to share between cores and the memory.... This is also the reason why any quad-core laptop chips will have lowest power crown go to amd- more buses, less speed per bus- after all, isn't that the selling point on why dual-core is superior to single?

I wanna see when there will no longer be an L2, and the CPU can simply use a partition of the ram just as quickly- talk about performance and power-saving there! (not to mention heat reduction!)


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