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Intel announces its “most energy-efficient Intel Core processor” to date

When it comes to processors used in today’s computers (be they laptops, desktops, or servers), Intel remains the king. However, as consumers find themselves increasingly moving away from being tied down to a desktop towards mobile devices, Intel still wants to be at the forefront of innovation when it comes to processor performance and efficiency.
 
With processors based on ARM architecture clearly dominating in the smartphone and tablet space, Intel is looking to push back heavily starting at the convertible PC level and downward. To show its commitment, Intel is introducing a new Core M processor that is based on the 14nm Broadwell architecture. Intel calls the Core M the “most energy-efficient Intel Core processor” to date, and states that the processor will enable a broad range of thin, lightweight, and more importantly, quiet mobile devices.


Intel's Llama Mountain reference design
 
Compared to the previous generation Core offerings, the Core M will have a 60 percent lower TDP, 20 to 40 percent better performance, and a 50 percent smaller package footprint.
 
At Computex, Intel demoed a 2-in-1 device with Core M, codenamed Llama Mountain, which pairs a 12.5” fanless tablet with a detachable keyboard. The tablet itself is just 7.2mm thin, and weighs 1.48 pounds. For comparison’s sake, the recently announced Surface Pro 3 features a 12” display, is 9.1mm thin, and weighs 1.76 pounds.

 Microsoft's Surface Pro 3 is 2.1mm thicker than the Intel reference design

One of the first products to use the new Core M processor is the ASUS Transformer Book T300 Chi which runs Windows 8.1. This convertible PC features a 12.5” IPS display (2560x1440), detachable keyboard, and integrated LTE connectivity.


ASUS Transformer Book T300 Chi
 
There’s no word yet on availability for the Transformer Book T300 Chi, or other devices that will use the Core M.

Sources: Intel, ASUS



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RE: Not much to go on here.
By Khenglish on 6/3/2014 3:13:29 PM , Rating: 2
Unfortunately for smaller processes, manufacturing is a smaller problem than physics of how a 10nm or smaller transistor can even work.

Here's the #1 problem:

http://ratnuu.files.wordpress.com/2010/09/mobility...

Carrier mobility (mu in the graph) is linearly related to how much current a FET can push. If you have half the mobility, then you have half the current. 10^18 dopant atoms per cm^3 already has a very large carrier mobility drop and is considered to be a high dopant level. Let's do the math on how many dopant atoms the body of a 10nm FET will have:

volume of transistor body: 10nm^3 = 10^-24 m^3
dopant atom concentration: 10^18atoms/cm^3 = 10^24 atoms/m^3

transistor body volume * dopant concentration:
10^-24 m^3 * 10^24 atoms/m^3 = 1 atom

yeah... 1 atom in the entire transistor body. This is not enough to make defined junctions between the body and the source and drain. To make matters worse, FETs only conduct current in a thin channel near the gate, so if we try doping a 10nm FET at 10^18 atoms/cm^3, the transistor is too small to have any dopant atoms in the channel . You could step up to a 10^19 atom/cm^3 dopant concentration, but then you just cut your transistor conductivity roughly in half, and that is still a low dopant count which will result in very high leakage.

As for FINFETs, all the math is identical. They do not fix this problem.

Oh and people may argue with me that the #1 problem is actually wire resistance. That gets worse linearly with every die shrink too.


RE: Not much to go on here.
By mik123 on 6/3/2014 4:46:35 PM , Rating: 2
Actually, 10nm process is considered feasible, and major players are already talking about 7nm:
http://www.eetimes.com/document.asp?doc_id=1322049

I do think however that 7nm or 5nm will be the last Si based process.

Good news is there's no shortage of alternative device technologies/materials (e.g. graphene looking good).

And of course, once they stop scaling they will start stacking, so Moore's Law is not in danger any time soon.


RE: Not much to go on here.
By Khenglish on 6/3/2014 8:24:25 PM , Rating: 2
I hope they figured out some workaround. Unfortunately I'm worried that they made out roadmaps for 7nm without trying to make the physics for the device work yet.

As for 10nm and under, I completely believe that the parts can physically be made and functional, but that the devices will be slower than 14nm devices.

As for graphine, yield is utterly impossible. You literally cannot have a single atom of variance. If you do that location of your semiconductor becomes a permanent conductor, or a permanent insulator. It is impractical for making a multi-billion transistor processor.

What could work is taking a FET and pulling the gate oxide turning it into a lateral BJT. My college (RPI) has simulated 32nm lateral BJTs at 1.3THz, which is 5 times faster than a 22nm FinFET. People refuse to look at this though since they hear "BJT" and think "that's old we won't even look at it" despite it being a completely different design from the old vertical BJTs. Going the BJT route doesn't solve the scaling problem though, it just immediately offers a faster device.

Going BJT though makes keeping current down problematic. While a single transistor is power competitive with a FET, chains are not without care. When having a chain of logic, the early logic needs to be low current since the current is multiplied by over 100 (beta) at each transistor. This can be used to save power since early logic can now be low power with the final logic meeting the current requirement, but it's still a new concern.


RE: Not much to go on here.
By Khenglish on 6/3/2014 8:35:58 PM , Rating: 2
I forgot about 3D:

3D is fun stuff and offers huge performance improvements. You can vastly shorten your interconnect lengths and integrate memory on-chip with orders of magnitude higher bandwidth than you can by going to even a modern L1 cache.

There's 1 big problem with 3D though, and that's heat density. If you take logic that has an area A, and stack it in 3 layers ontop of itself your logic now has 3 times the heat density. A 22nm CPU without an overclock already has about a 30C temperature differential between the die and heatsink due to how small the high-power area of the cores are. Stack the logic on itself 3 times and you now have 90C just across the thermal interface. A big part of this is because for some reason we still use Silicon Dioxide to physically protect the processor which has around 1/100th the conductivity of copper, but stacking only makes the heat density problem worse.

Overall I think it is a good idea to do 3D. There are ways to bond the wafers with very high yield. As with everything though, there's always a drawback. This problem should be fixable by ditching SiO2 as the processor's protective coating for something more thermally conductive.


RE: Not much to go on here.
By mik123 on 6/4/2014 3:04:49 PM , Rating: 2
Regarding the heat problem in 3D, I'm wondering why not just slow down the clock?

For example, what if you could get rid of DRAM entirely, and put a couple of GB of SRAM on die (say 20 layers on top of logic)? This way, the program would load from SSD straight into SRAM on the CPU. You would still want to have a couple of levels of cache, but your main memory accesses would speed up dramatically.

To deal with heat from those 20 layers of SRAM and the CPU, slow the clock to, say, 500 MHz. Sure, the CPU becomes slower, but the main memory is now at least 10 times faster, and system design is simplified.

Also, a slower clock allows to have multiple layers of logic too, so a multilayer CPU can have more transistors: cram more cores, more execution units per core, larger graphics accelerator unit, etc.

Finally, a slower clock allows to build larger, more complex systems, because it's much easier to deal with signal integrity issues.

If 500 MHz sounds like an awfully slow speed, just remember that your brain works pretty well at just 100 Hz.


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