Intel's Broadwell Will Likely Slip Past Back-to-School Shopping Season
May 19, 2014 5:22 PM
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First 14 nm chip will likely not be ready until the holiday shopping season, after defect issues
Before 2013, Intel had seen several years of aggressive updates to the Core i-Series. Each spring would
bring fresh announcements of "ticks"
(architecture refreshes), which would alternate on a yearly basis. By the summer months, these chips would have
found their way into high-end laptop models
I. The Slippage
But eyed more carefully, signs of slippage to Intel's breakneck pace have been showing.
, the second generation of Core i-Series processor
launched in Jan. 2011 (Q1 2011) and began shipping almost immediately.
-- the third generation Core i-Series chips
-- were released a bit later, right at the start of Q2 2012 in April 2012. As the release -- a die shrink to 22 nanometers -- brought the tricky-to-manufacture 3D FinFET technology to the table, most wrote off this slippage as natural.
, Intel's 22 nm architecture refresh, slid back a few more months to June 2013. Some did notice this time, with rumors mounting that the die shrink to 14 nm --
might be delayed until 2015
. It turned out the reports were somewhat true -- Intel was suffering much higher defect rates than previously expected -- but Intel insisted that
chips would be
delayed only a quarter, to Q1 2014
But Q1 2014 (Jan. to Mar.) came and went and
still was a no-show in terms of shipments to OEMs. In an April 2014 earnings call, CEO Brian Krzanich insisted that the wait was almost over, saying that the chips would ship sometime in H2 2014. Most hoped this might mean Q3 2014, in time for the August-September back to school shopping season.
Intel CEO Brian Krzanich [Image Source: Intel Russia]
However, while attending the
in San Mateo, Calif. this past Saturday Mr. Krzanich
delivered some disappointing news
. His comment hints to investors and customers not to get their hopes up of seeing
product shipping in time for that key sales season.
I can guarantee for holiday, and not at the last second of holiday. Back to school - that's a tight one. Back to school you have to really have it on-shelf in July, August. That's going to be tough
If the Nov.-Dec. shipping window (perhaps with a September soft launch at the Intel Developer Forum) proves accurate, Intel will have lost nearly a full year in terms of slippage over the past four launch cycles, starting with
Broadwell should be available in time for the holidays.
This slippage originates from the high defect rates that every chip fab company encounters when moving to smaller nodes. Intel typically tapes out test runs of chips and then must make the difficult decision of what will cost more -- the chips scrapped due to defects for the present process, or the cost of waiting and pushing back the refresh. No matter what Intel chooses a fair amount of chips will be lost to design flaws, the trick is minimizing that number.
II. The Danger
pocketing around $2.5B USD in profit per quarter
, so it's not exactly hurting for cash. Still, having narrowly
missed on its last two outlooks and struggling to gain ground in the mobile space
, there's fear that the world's largest PC chipmaker may see its PC and server market share gobbled up by fresher competitors.
One of Intel's most dangerous rivals
is the Taiwan Semiconductor Manufacturing Comp.
, Ltd. (
) (TSMC). TSMC is expecting to tape out 16 nm FinFET transistor-based chips late this year, possibly in Q4 2014. If all goes well, this 16 nm product could launch as early as the 2015 back-to-school shopping season. If it can pull that off, it may have closed the gap with Intel to about a year, versus
the gap of over two years process-wise that existed back in 2011
TSMC is preparing 16 nm FinFETs for a late 2014/early 2015 launch. [Image Source: Cult of Mac]
Another key rival is Samsung Electronics Comp., Ltd. (
). Having taped out 14 nm transistors in Dec. 2012 in a test run, Samsung has been
working to mature the technology at its fabs
. Samsung has teamed up with former Advanced Micro Devices, Inc. (AMD) spinoff, Global Foundries to push the technology into production. According to
The EE Times
, production is expected to begin in late H2 2014, and product may be available late in the holiday season.
Samsung and GlobalFoundries hope to ship 14 nm FinFET product by the end of 2014, as well.
That same article, though, added a grain of salt courtesy of market analysis firm International Business Strategies Inc. (IBS). Handel Jones, the firm's chief, told the publication:
IBS is expecting foundry-fabless companies also will experience delays on FinFETs similar to Intel. Also, Intel has experience of FinFETs at 22 nm, and foundry-fabless companies do not have same expertise.
So don't be surprised if third-party fabs aren't quite caught up yet with Intel when 2015 rolls around.
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Why are we still using CMOS?
5/19/2014 10:43:48 PM
Any word on anyone adopting complimentary lateral bipolar devices? The switch solves all major problems with CMOS, which are inadequate channel doping (there is no longer a source-body or body-drain PN-junction boundary at 14nm and under at ideal doping levels), minimum thin oxide thickness (we've been at since 32nm. This is why Intel's 22nm and 32nm chips ran at the same voltages), and poor current drive for ever increasing wire resistance (process shrink drops wire thickness).
Lateral bipolars push 4 times the current at the same size as a FET to combat rising interconnect resistance, maintain switching times, while having zero leakage (SOI prevents base leakage, exponential turn-on prevents off-state leakage), and lack a thin-film oxide so they will have higher yield. Yes they draw base current, but beta for a lateral bipolar is over 100. As for base current being multiplied so that current draw is too high, good. That means you can decrease wire thickness and increase dopant levels allowing the device to be shrunk down for future process nodes, something that CMOS currently cannot do.
And that's on Silicon. Since this would drop the thin oxide there is no reason to use Silicon, thus allowing Germanium to be used instead to cut the voltage by 40%.
They do require a boxed transistor (SOI) though, but dropping the thin oxide for a backside oxide should be a roughly even tradeoff.
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