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Native quad-core en route

Yesterday during AMD's Q2'06 earnings conference call, AMD's President and Chief Operating Officer Dirk Meyer recapped the long term plans for the company.  Although the bulk of his comments were already stated in during the June AMD Analyst's Day, Meyer also added the tidbit that the company plans "to demonstration our next-generation processor core, in a native quad-core implementation, before the end of the year."  Earlier this year, AMD's Executive Vice President Henri Richard claimed this native-quad core processor would be called K8L.

Earlier AMD roadmaps have revealed that quad-core production CPUs would not utilize a native quad-core design until late 2007 or 2008. To put that into perspective AMD demonstrated the first dual-core Opteron samples in August 2004, with the processor tape out in June 2004.  The official launch of dual-core Opteron occurred on April 21, 2005.  On the same call Meyer announced that that the native quad-core would launch in the middle of 2007 -- suggesting the non-native quad-core Deerhound designs may come earlier than expected or not at all.

Just this past Wednesday, Intel one-upped K8L plans by announcing quad-core Kentsfield and Clovertown will ship this year, as opposed to Q1'07 originally slated by the company. 


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RE: Trying to step out of the shadows?
By stmok on 7/22/2006 10:21:44 AM , Rating: 1
You really have to get off your high horse.

What's this nonsense about "marketing hype" of intergrated memory controller and HyperTransport?

Intel is gonna be adopting a similar implementation to HyperTransport. Its called CSI.

And what about the integrated memory controller? Intel has done that before, they screwed up. The project/CPU was called "Timna", and it used a integrated memory controller for RDRAM. ("Timna" was the cancelled predecessor to "Banias"). Both designs were done by the same Israeli Intel team. With the "Banias", they used the PIII-S as the basis, and expanded on that. If you really think about it, Conroe is a descendent of the P6. (Pentium Pro, PII, PIII, Pentium-M, Core Solo/Duo).

Intel has improved the instructions per clock and prefetching such that Conroe is the "delaying mechanism" for future Intel CPUs that will integrate CSI and possibly a memory controller. (As in they've done enough to keep AMD back for now, while their R&D work on something new and experiment with new ideas).

Even an Intel engineer admitted an integrated controller is a good idea. (They aren't sure if they're really gonna need it yet...But they are considering it in a future design).

AMD's Hypertransport or Intel's CSI is a good idea as we increase the number of cores into the future. If you've bothered to look in the 4-core or CPU market, you'll see Intel's current bus design has a bottleneck in this scenario. (And you'll see a situation where Conroe-based solutions will be held back by the bus design).

That's why the Xeon version of the Conroe will have dual-independent buses! (one for each dual-core CPU). And its also why AMD is very likely to hold onto the 4-core/CPU market until K8L comes.

You really should get a good feel of CPU history and upcoming ideas before blabbering nonsense to make yourself feel better about Intel. Because you currently sound like a no clue fool.


By masher2 (blog) on 7/22/2006 1:29:02 PM , Rating: 2
> "Even an Intel engineer admitted an integrated controller is a good idea"

Actually, several Intel engineers have 'admitted' what anyone in the industry already knew. That an integrated memory controll is a classic tradeoff scenario...with good points and bad. Intel has toyed with them several times, but decided the benefits weren't worth the disadvantages. AMD decided the opposite. And-- given the differences in the architecture of each-- it can very well be that BOTH companies made the right decision.


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