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Samsung also is eyeing Cortex-M processors for its Smart TVs and appliances

Two of the smartphone market's biggest powers met this week to discuss processors.  UK-based ARM Holdings plc (LON:ARM), an architecture company whose titular instruction set is found in 95 percent of smartphones sold today, traveled to South Korea, the home turf of Android phonemaker South Korea's Samsung Electronics Comp., Ltd. (KSC:005930).  Samsung accounted for over 30 percent of global smartphone shipments in Q3 -- nearly three times more than any other OEM.
 
Samsung and ARM met to discuss the adoption of ARM's new ARMv8 64-bit instruction set, which Samsung's upcoming Exynos 6 processors for next year's Galaxy S5 is expected to use.  Antonio Viana, ARM’s executive vice president of commercial and global development, met with senior Samsung executives to talk about the roadmap to 64-bit and beyond.
 
An unnamed senior manager at ARM with knowledge of the meeting suggested 128-bit chips might also have been discussed.  While PC CPUs have yet to hit 128-bit, The Korea Herald quotes the senior ARM executive as saying there was a "possibility" that ARM would release a 128-bit instruction set in the next two years and push for smartphone/tablet adoption.  But the Korean publication says the ARM official said these plans were only a "possibility" and not a definite plan at present.
 
Exynos
Samsung wants to make sure that its Exynos chips for next year's Galaxy S5 have access to ARM's best instruction set -- the 64-bit ARMv8 instruction set.

The official is quoted as suggesting that smartphones soon may have more than 4 GB of memory and need 64-bit processors to address their memory.  The source stated, "As technology moves from, for example, shifting to face recognition on smartphones from the fingerprint scanner to unlock an iPhone, it requires more powerful memory capacity."
 
It also appears that ARM is incentivizing the transition to 64-bit ARM chips in the mobile market, in part, to fuel its server ambitions, as well as its PC push.  
 
While 64-bit chips offer some gains in graphics and I/O addition to the aforementioned memory addressing gains, processing is generally otherwise unaffected.  However, ARM is purposefully tilting the playing field in 64-bit's flavor by designing its new instruction sets -- which allow more registers -- to only work for 64-bit chips.  32-bit chips will be forced to use the older, less optimized ARMv7.  In other words, ARM is telling mobile chipmakers to make the switch or settle with last generation instruction sets.
 
This push will allow ARM to foster an ecosystem of compatible applications, which may help the chip designer to push into the PC and server markets, two key areas of desired growth.

Cortex M
Samsung may look to use the Cortex M chips in new appliances.

Samsung and ARM also reportedly discussed the Cortex-M processor, a low power core design which Samsung may look to use in its appliances and Smart TVs.

Source: The Korea Herald



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RE: 128-bit?
By coburn_c on 11/21/2013 4:33:23 PM , Rating: 1
Floating point math can benefit from huge address spaces, integer math... no

That's why the 128-bit registers are in the FPU

The article spells it out, ARM pushed 64-bit to phones to finance their desktop battle, wasn't needed on phones. 128-bit frontend isn't needed at all, it's just to grab headlines.


RE: 128-bit?
By inighthawki on 11/21/2013 6:07:24 PM , Rating: 2
Huh? What you said makes absolutely no sense. floating point operations do not have any special benefits from address space whatsoever. Memory is memory, just treated differently.

The 128 bit XMM SIMD registers on the x86 platform is for parallel data processing. It allows you to process 2x64bit or 4x32bit values at a time in a single instruction - hence the name Single Instruction Multiple Data (SIMD). As of SSE2 Intel already had integer versions of all of the instructions, even going a step further with 16x8bit and 8x16bit instructions for integers as well. But more importantly, those 128 bit registers do not do 128bit floating point math, nor do they have ANYTHING to do with address spaces.


RE: 128-bit?
By coburn_c on 11/22/2013 2:13:39 AM , Rating: 2
Vector processing is pretty much only used for FP math. SSE was actually all originally integer functions. Commands that perform the same function on multiple data sets all prefer FP math. That was not the case when CPU FP was on an outside chip.. but these days... If you look inside any modern processor the 128-bit registers exist in the FPU. The FMAC performs the SIMD instructions in fact, using FMA3. Two guesses what those Fs stand for.


RE: 128-bit?
By inighthawki on 11/22/2013 3:21:52 AM , Rating: 2
quote:
Vector processing is pretty much only used for FP math

Commonly especially in games and scientific work, but integer is not at all rare. You can use integer based SIMD instructions for processing things like strings. In fact I've used SSE2 based integer instructions to implement string length functions that are an order of magnitude faster than standard non SIMD based implementations. I would also kill for the ability to have 128bit integer instructions to do things like comparing a GUID with a single compare.

quote:
SSE was actually all originally integer functions.

No, it was not. SSE1 was all FP. SSE2 added integer. Try again. Maybe you're thinking of MMX, which was 64-bit and superseded by SSE2. (SSE had a couple integer instructions that operated on the MM registers)

quote:
That was not the case when CPU FP was on an outside chip.. but these days... If you look inside any modern processor the 128-bit registers exist in the FPU.

In most cases this is only because the SIMD instruction sets may not actually have integer instructions for them. So duh, of course they will be in the FPU.

quote:
The FMAC performs the SIMD instructions in fact, using FMA3. Two guesses what those Fs stand for.

FMA3 , you mean the ' F used' M ultiply A dd 3 instruction set?


RE: 128-bit?
By coburn_c on 11/22/2013 3:41:26 AM , Rating: 2
Fused, meaning single precision, as in floating point.

To bring this full circle, 128-bit SIMD registers does not a 128-bit chip make, or all current chips would be considered 128-bit... and outside of SIMD what purpose is there for 128-bit silicon?


RE: 128-bit?
By coburn_c on 11/22/2013 3:43:22 AM , Rating: 2
Oh, and ARM has 128-bit SIMD already, it's called NEON


RE: 128-bit?
By inighthawki on 11/22/2013 11:12:44 AM , Rating: 2
What is your point? This has nothing to do with the point I'm trying to make. I'm WELL aware of what NEON is, as well as SSE, AVX, PPC's altivec. They're all SIMD instruction sets... so?

128-bit SIMD is not the same as 128-bit processing. There is a difference between process 4 32 bit elements and a single 128 bit element at once.


RE: 128-bit?
By otherwise on 11/22/2013 10:40:45 AM , Rating: 2
Fused, meaning there is no intermediate rounding step; i.e. if you think of floating point error as a e() function -- the result is e(x(y+z)) instead of e(e(y+z)*e(x)). The fact the operation can be optimized to be faster than a=y+z; b=e*x is a bonus.


RE: 128-bit?
By inighthawki on 11/22/2013 11:11:10 AM , Rating: 2
I made it very clear in my initial post that 128-bit SIMD registers was NOT the same thing as processing 128 bit data elements.

quote:
and outside of SIMD what purpose is there for 128-bit silicon?

Faster processing of anything that uses 128 bit data. Cryptography, GUID processing, hashes, etc.


RE: 128-bit?
By inighthawki on 11/22/2013 11:22:50 AM , Rating: 2
quote:
Fused, meaning single precision, as in floating point.

It's become even more apparent that you don't know at all what you're talking about. Please don't post useless garbage unless it's actually accurate. First you think (or incredibly heavily imply) that the F stood for float, and now you think 'Fused' is synonymous with single precision floating point? A simple trip to Wikipedia to look at the FMA3 instruction set shows that it has double precision instructions lol. Oh but see, you probably have never used them so you wouldn't have known that the PS and PD suffixes on the instructions stood for 'packed single' and 'packed double,' so that's an easy mistake. (Or 'scalar single' and 'scalar double' for the SS/SD variants if you didn't know those either)

quote:
To bring this full circle, 128-bit SIMD registers does not a 128-bit chip make, or all current chips would be considered 128-bit...

I didn't say it did at all. Please go back and (carefully) reread my original posts. Not once did I claim that SIMD meant that these were '128 bit processors.' Quite the opposite in fact.


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