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SMP version of "Conroe" takes flight, but availability seems scarce

This Monday, June 26, 2006, Intel will launch its new Woodcrest processor, a server processor based on Intel's Core architecture. The new processor family, dubbed Xeon DP, will use Socket LGA-771 and include support for multiple-CPUs -- which enables a system to support more than one Woodcrest processor, as opposed to being limited to just a single Core 2 processor per system. Despite the significant difference, every other aspect of Woodcrest is virtually identical to Core 2 Duo for the desktop.

Intel's new Woodcrest processor comes at us with the intention to compliment and ultimately replace Dempsey, Intel's latest dual-core Xeon processor based on the NetBurst microarchitecture. While both Dempsey and Woodcrest are based on 65nm processes, Woodcrest will focus a great deal on power consumption efficiency.  Both Dempsey and Woodcrest have a TDP envelope of 130W, but the performance is much higher on Woodcrest giving better performance-per-Watt. Being a NetBurst component, Dempsey scaled high in clockspeed, reaching up to 3.73GHz on a 1066MHz FSB. It also employed a 2x2MB L2 cache structure versus Woodcrest's shared 4MB L2 cache. Another detail to note is that Dempsey is capable of processing up to four threads simultaneously thanks to Hyper-Threading, versus Woodcrest's maximum of two -- Hyper-Threading is not enabled on the first Core 2 Duo nor Woodcrest Xeons.

During some demonstrations of Woodcrest
, Intel stated that when compared to AMD's Opteron processor, Woodcrest can be up to 33% more efficient in power consumption. Actual tests however indicated that Woodcrest is about 10% to 15% lower in some situations.  As for evolution, Intel says that the new Woodcrest is two to three times better in power efficiency over the previous Dempsey core.  AMD also recently published its opinion on server power consumption.

Unfortunately, here's the kicker.  Numerous channel vendors have contacted DailyTech claiming that availability of Woodcrest will not be for another two weeks.  Synnex and ASI will be the only US distributors with any quantity, and then general availability begins WW31. One vendor sent DailyTech a memo claiming "[the] second week of August is when we start to get box [processors] in volume." Several vendors will announce system builds with the processors immediately, but there will be no channel availability.  Motherboards are already widely available as every Socket 771 motherboard that supports Dempsey also supports Woodcrest.  Intel will ship Woodcrest Xeon DP in the following configurations:

Intel Xeon Processor

Core /
L2 Cache
Price @
Xeon Processor DP
(Woodcrest Bin-0)
5160   3.0GHz /
Xeon Processor DP
(Woodcrest Bin-1)
5150   2.66GHz /
Xeon Processor DP
(Woodcrest Bin-2)
5140   2.33GHz /
Xeon Processor DP
(Woodcrest Bin-3)
5130   2.0GHz /
Xeon Processor DP
(Woodcrest Bin-4)
5120   1.86GHz /
Xeon Processor DP
(Woodcrest Bin-5)
5110   1.60GHz /

All Woodcrest processors will sport 4MB of L2 cache and are manufactured at 65nm. Prices will start at $210 and increase up to $850 in batches of 1000. With Woodcrest it's evident that most if not all of the world's top server companies will be shipping systems with the new processor. One of the most anticipated uses of Woodcrest will be Apple, which is expected to be releasing Woodcrest based systems later this year.

will be accompanied by DDR2 memory, running at either DDR2-533 or DDR2-667. On Intel's Bensley platform, Xeon DP systems will be limited in the graphics department -- systems will only support a single-lane PCI Express setup. However, memory performance should see a nice boost thanks to the use of fully-buffered DIMMs (FB-DIMMs).

Looking further down the road, Intel's Clovertown will feature quad-cores -- two Woodcrest dice stamped onto a single package. This gives Clovertown systems the ability to scale up to eight CPU cores. Intel also says that Clovertown will deliver power consumption levels on par with Woodcrest. Later this year, Intel will also release Xeon MP Tulsa, the final processor based on the NetBurst architecture. Tulsa may be the last NetBurst processor from Intel, but it will be the company's first x86 processor to support shared L3 cache.  Intel's Itanium 2 Montecito processor will be the company's first shared-L3 processor.

Looking through into 2007, Intel is expected to introduce Tigerton, a new Xeon MP processor set to replace Tulsa. Tigerton is expected to contain at least four cores and have support for SMP configurations of four or more processors per system. With Tigerton, Intel is also expected to include a technology it currently calls "dedicated high-speed interconnect." The new technology gives each processor a direct pathway to the chipset. This will prove to be much faster than today's front-side bus technology. Actual launch dates for Tigerton are still unknown.

AMD also has a big server release around the corner on August 1, 2006. The new Opteron "Revision F" -- based on LGA 1207-pin Socket F -- will mark a significant evolution in multi-core CPUs for AMD.

Update 06/26/2006: The Intel press relese for Woodcrest was released today.

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By maevinj on 6/23/2006 2:43:30 PM , Rating: 2
I know I'm a dumba$$, but I'm confused why intel is releasing so many different server cores in a relatively short time. I could just imagine the confusion on the dell website trying to by a server and thinking you're getting x core and actually get y core

RE: confused?
By TheDoc9 on 6/23/2006 3:09:57 PM , Rating: 3
There trying to erase their past mistakes. Problem is obviously availability. We'll have to wait a few more weeks, but it wouldn't surprise me to see extreemly short supplies and high markups for these chips.

Dedicated HS Interconnect
By vgermax on 6/23/2006 3:13:25 PM , Rating: 2
Starting with the i5000P (Blackford) chipsets, Intel now has two independent FSBs available, one for each socket. This alleviates, to a certain degree, the limitations of shared bus architecture. However, when there are multiple die per socket all the die present share one bus from the socket. AMDs implementation for multiple core CPUs remains superior in this regard. I would think this approach of multiple FSBs from a single northbridge is a stop-gap solution, although apoint-to-point interconnect from Intel seems terminally delayed.

RE: Dedicated HS Interconnect
By hstewarth on 6/23/2006 3:31:38 PM , Rating: 2
The article states that high speed interconnect is for Tigerton which comes in 2007. This is called CSI in intel terms.

RE: Dedicated HS Interconnect
By Zanfib on 6/23/2006 3:42:17 PM , Rating: 2
For sure.

AMD has the advantage of the onboard memory controller too, meaning there is quite a bit less traffic on the FSB/HT links then if the memory controller is on the motherboard. I agree HT is the more elegant solution though, even if memory traffic doesn't always need to go over it, when it does (to memory located on another socket's controller) HT is nice and fast, and scaleable.

Woodcrest has a fair amount of FSB to play with though, 1333 MHz when the cores are running a fair amount slower (compared to the 3.73 GHz Xeons) will help, but certainly only until clock speeds start increasing or both cores really want to use the FSB at the same time).

RE: Dedicated HS Interconnect
By hstewarth on 6/23/2006 3:53:36 PM , Rating: 2
But there is more than just the high speed bus of the Woodcrest. It also has FB-Dimm memory which reduces the need for memory controller - because of interface to memory.. which is suppose 4x the normal memory speed.
I belive the FB-Dimm serial memory is designed to reduce the overhead on the bus on memory - just like SATA compared to PATA does.

Intel does have in plan Intergrate memory controller which combine with higher speed bus and FB-Dimm memory should help a lot.

I think memory test have shown that its almost as good as AMD's.

The fact that the woodcrest cores are slower compared to 3.73 ghz xeon is a good thing, on 1333Mhz bus, this means that we have are going to have a lot faster Woodcrest in the future.

RE: Dedicated HS Interconnect
By Viditor on 6/24/2006 11:48:03 PM , Rating: 2
It also has FB-Dimm memory which reduces the need for memory controller - because of interface to memory.. which is suppose 4x the normal memory speed

I think you are confusing bandwidth with throughput.
FBDs are capable of writing and reading simultaneously, but there is no reduced need for the memory controller, and it certainly doesn't reduce the "overhead on the bus" (not really sure what that means though...).

RE: Dedicated HS Interconnect
By Viditor on 6/25/2006 10:28:40 AM , Rating: 2
The article states that high speed interconnect is for Tigerton which comes in 2007. This is called CSI in intel terms

Nope...the CSI interface is coming out in 2008/9. The high-speed interface they are talking about is the dual FSB.

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