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New processes push technology to the verge of commercialization

International Business Machines, Inc. (IBMis among the companies racing to develop nanophotonics -- on-die light based signaling components -- which can be incorporated directly side-by-side with traditional silicon-based electronics using traditional manufacturing techniques like complementary metal-oxide semiconductor (CMOS).

Currently, signals between components like the processor cores and the memory crawl along as electrons along copper-based wires.  In the new scheme modulators (which create the signal, often using a ring), wave-length multiplexers (which route signals), switches (which turn signals on or off), and detectors (which receive signals) are baked onto silicon chips connected by fiber optics.  Signals then travel at the speed of light along fiber optic channels.

After first demoing the technology in crude proof-of-concept form back in 2010, IBM has returned with the world's smallest announced CMOS-compatible nanophotonics processes.  The company showed off chips this week that were build on a traditional 90 nm CMOS node, a node far smaller than earlier prototypes.

IBM wave guide
Blue optical wires are shown accelerting the "slow" copper wire (orange) traffic.

IBM says the technology is "primed for commercial development" and will soon be ferrying "terabytes of data between distant parts of computer systems".  In a demo IBM showed off 25 gigabytes-per-second (GBps) transfer rates, a speed typically seen in bulky telecommunications fiber-optics equipment, not in PC interconnects, which crawl along at megabytes-per-second (or around 1 Gbps for high-speed PCI-express lanes).

The hope is that the new interconnects will soon pump internal and external communication up to speeds of up to thousands of times the current technology.

Dr. John E. Kelly, Senior Vice President and Director of IBM Research, remarks, "This [latest showcased] technology breakthrough is a result of more than a decade of pioneering research at IBM.  This allows us to move silicon nanophotonics technology into a real-world manufacturing environment that will have impact across a range of applications."

The IBM research fellow and SVP will be showing off his work in a paper at the IEEE International Electron Devices Meeting (IEDM), which is being held this week in San Francisco, Calif.

Sources: IBM [1], [2]



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RE: Bandwidth
By KentState on 12/10/2012 1:19:48 PM , Rating: 3
Every lane would be 25GB/s. Hopefully fewer lanes would lead to less complex motherboards.


RE: Bandwidth
By Egglick on 12/10/2012 1:40:55 PM , Rating: 2
Yeah, a single 25GB/s lane would be enough for most any current consumer-level addon card. The biggest benefit would be to the System RAM though. This sort of technology would both drastically increase bandwidth, and also lower latency to almost nothing. You could theoretically see system RAM which comes close to the speed of the CPU's onboard cache.


RE: Bandwidth
By jdietz on 12/10/2012 4:13:04 PM , Rating: 2
No it won't. It'll be closer to being a "true" L4 cache.

Modern system latency:
Register: Next cycle
L1 Cache: 4 cycles (Ivy Bridge)
L2: 12 cycles (Ivy Bridge)
L3: 24 cycles (Ivy Bridge)
RAM: 133 cycles (Ivy Bridge @ 3.4GHz)

This tech may help reduce RAM latency. Not sure exactly how much. Other tech might help more at reducing latency, like phase-change RAM.


RE: Bandwidth
By Egglick on 12/10/2012 6:17:35 PM , Rating: 2
Of course I'm not talking about using existing DRAM technology. You would want to design something entirely new in order to take advantage of the exponentially faster interconnects.


RE: Bandwidth
By Digimonkey on 12/10/2012 6:47:08 PM , Rating: 2
Is that really the case? You usually don't measure a serial connections in bytes.


RE: Bandwidth
By Digimonkey on 12/10/2012 6:51:13 PM , Rating: 2
Nevermind, I see it was meant to be 25 Gigabits.


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