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New memory recycles last-gen process, but still offers 30 percent performance gains

Embedded MultiMediaCard (eMMC) -- tiny chips soldered to smartphone and tablet motherboards via ball-grid arrays -- are a staple of the mobile industry.  Samsung Electronics Comp., Ltd. (KSC:005930offered up some exciting news today, revealing that it had started production of 10 nm-class (10-19 nm) NAND for eMMC, taking mobile storage to new levels of "tiny".

The new 64 GB NAND Flash storage chips, which are built on the eMMC 4.5 standard, which Samsung basically wrote itself, offer random writes of 2,000 IOPS (input-output operations per second), random reads of 5,000 IOPS, sequential reads at 260 MB/s, and sequential write speeds of 50 MB/s.

Those stats are about 30 percent up from the first-generation eMMC 4.5 devices (mature 20 nm product), which Samsung delivered five months ago.

More good news for Samsung is that it was able to repurpose its 20 nm lines to produce the 10 nm-class chips.  It says the process compatibility is expected to increase its manufacturing yields around 30 percent.

Samsung NAND flash
Samsung is now producing NAND on the 10-19 nm node. [Image Source: Samsung]

Samsung also shaved over 20 percent off the volume off the traditional 12 mm by 16 mm flash BGA package, squeezing the chips into a 11.5 mm by 13 mm form factor.  The chipmaker, having deeply invested in development of eMMC 4.5 is looking to submit it to JEDEC (the Joint Electron Engineering Council), next year, requesting that it be made an industry standard.

Recently, there has been controversy regarding Apple, Inc. (AAPL) being forced to pay more for Samsung's chips, in the wake of its decision to continue to attack the better selling smartphone maker in court.  The new 10 nm-class Flash chips are likely enough to leave Apple -- purveyor of all things thin -- salivating, but they may be another opportunity for Samsung to extract a piece of fiscal revenge on its dependent rival. 

Source: Samsung [press release]



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RE: Don't feed the hype
By Shadowself on 11/16/2012 8:23:47 AM , Rating: 2
quote:
All in all, these chips are probably either 19 nm or 16 nm (a node Intel is aiming for), but highly doubtful 10 nm (unless Samsung has had some unbelievable, revolutionary breakthroughs in the past year).
My understanding is that Intel is shooting for the 14 nm node for its main products, down from its current main node of 22 nm.

Intel's NEXT projected node after 14 nm is 10 nm, but that is not planned to go into full production for at least three years.
22 nm: late 2011 through late 2013
14 nm: late 2013 through late 2015
10 nm: late 2015 through late 2017

This assumes that each half of Intel's "Tic-Toc" pattern stays at roughly 12 months, though it seems to be heading to more of a 15 month half step. If the slips keep happening -- which is likely at the 14 & 10 nm steps, then full production on Intel's main lines probably won't happen for the 10 nm step until mid 2016 or later.


RE: Don't feed the hype
By MozeeToby on 11/16/2012 9:09:19 AM , Rating: 2
Less than 11 nm is probably not even theoretically possible. And yes, I know that people have said that about many things over the years when it comes to process shrinks, so hear me out.

Quantum tunneling is the phenomenon where a particle (usually an electron) can disappear from one place and appear in another without crossing the intervening distance. The effect is completely random, you can't control it or shield against it. At around 11nm you reach the point where electrons jump across your gap at a rate that is indistinguishable to having no gap at all.


RE: Don't feed the hype
By geddarkstorm on 11/16/2012 3:33:28 PM , Rating: 2
Oh cool, you're right. They changed from a 16/11 aim to a 14/10 aim just recently. http://news.softpedia.com/news/Intel-s-16nm-Became...

As the poster below you says though, at around 11 nm quantum mechanics begins to disagree... so how they can get around that, if it is even possible with current styled silicon transistors, is.. going to be fascinating.


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