IBM Cooks up Process to Precisely Plant Aligned Carbon Nanotubes on Chips
October 29, 2012 1:59 PM
New ion-exchange based method can accurately place nanotubes at a density of up to 1B per square cm
Top players in the electronics industry have expressed increasing interest in using novel carbon materials, such as carbon nanotubes
to build transistors. Earlier in 2012, researchers at International Business Machines, Inc. (
), demonstrated a sub-10 nanometer
transistor using aligned carbon nanotubes
(CNT). Early tests on it showed that it could be 5 to 10 times faster than current 22 nm or 32 nm silicon-based transistors.
I. Growing Nanotube Transistors
But earning that speed improvement would be no easy task. The problem is that processes to sculpt aligned CNTs into circuits are still
in their very rudimentary stages.
But IBM has
a new mass-processing process that is capable of depositing aligned carbon nanotubes with precision at densities two orders of magnitude larger than ever before (1 billion CNTs per cm
The process, which falls under the ion-exchange category, starts with sucking CNTs up into water via the addition of surfactant (soap). The solubilized CNTs are then exposed to chemically modified hafnium oxide (HfO2) and silicon oxide (SiO2) "trenches". The CNTs align and bond to surface.
Carbon nanotubes "stick" to the hafnium trenches. [Image Source: IBM]
IBM tested the process to "grow" chips of up to 10,000 aligned CNT transistors.
II. Creeping Closer to the Real World
The larger circuit size is not only desirable from a standpoint of moving the tiny transistors closer to appearing in real world devices; they also solve a chicken-or-egg sort of problem by allowing more accurate performance measurements by using high-volume characterization tools.
Supratik Guha, Director of Physical Sciences at IBM Research, praises the work, stating, "Carbon nanotubes, borne out of chemistry, have largely been laboratory curiosities as far as microelectronic applications are concerned. We are attempting the first steps towards a technology by fabricating carbon nanotube transistors within a conventional wafer fabrication infrastructure."
IBM researcher Hongsik Park helped develop and test the new CNT circuit assembly technique.
[Image Source: IBM]
"The motivation to work on carbon nanotube transistors is that at extremely small nanoscale dimensions, they outperform transistors made from any other material. However, there are challenges to address such as ultra high purity of the carbon nanotubes and deliberate placement at the nanoscale. We have been making significant strides in both."
The research was
in the prestigious peer-reviewed journal
IBM [press release]
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