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Intel's Kentsfield CPU (top) will be the first quad core desktop chip, Clovertown will be the server equivalent - Courtesy AnandTech.com
Intel talks of quad-core Xeons and shares thoughts on integrated memory controllers

A newly invigorated Intel is pulling out all of the stops to stay ahead of AMD these days. Intel's Core 2 Duo Extreme is putting out some rather encouraging numbers and should keep AMD working hard for the next few quarters. And shortly after aggressive pricing was revealed for Intel's new Core 2 family of processors, AMD responded with its own price cuts across the board to stay in the game. With its mainstream desktop products taken care of, and its new Core 2 mobile processors on the way, Intel is looking forward to updates to its server processors.

Intel's Woodcrest processors look to make up for the sins of the father, in this case the current Xeon, by increasing performance by 80% while lowering power consumption by 35%. Even more impressive is Intel's ramp of the Woodcrest -- by the end of 2006, Intel is expecting that 90% of the Xeon processors that it ships will be dual core. Two thirds of those dual-core offerings will be Woodcrest based according to Intel.

Just around the same time that Intel releases its quad-core Kentsfield desktop processors in Q1'07, quad-core Clovertown server processors will also make an appearance. According to Intel's Enterprise Architecture Director Dileep Bhandarkar, Clovertown will be two dual-core processors built into a single package versus AMD's single package of four cores. Bhandarkar also conceded that the lack of an integrated memory controller, like those on the AMD64 platform, does hurt performance. EWEEK reports:

Bhandarkar admitted that integrating the memory controller—which handles the flow of data to and from system memory—directly into the chip rather than housing it on a chip set would improve performance with some workloads. However, he said, Intel officials felt it was more important to bring a quad-core processor to the market before AMD does. The company expects to precede its rival by a quarter or two.

Still, Bhandarkar feels that its server products will offer enough of performance advantage that it won’t need to delve into integrated memory controllers for now. In the mean time, integrated memory controllers are definitely in the pipeline as is an integrated graphics controller, but no timeline was given for either.



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RE: CSI/Hypertransport?
By czarchazm on 6/14/2006 9:58:01 AM , Rating: 2
quote:
I can name two technologies right off the top of my head that Intel has borrowed from AMD, namely and on-die memory controller
...

Dude, that's like saying Kodak's CMOS is using Nikon's technology because it is an imager type. On-die memory controller is just another implementation of the controller.



RE: CSI/Hypertransport?
By Viditor on 6/14/2006 12:13:58 PM , Rating: 2
quote:
On-die memory controller is just another implementation of the controller

It's not, actually...AMD's on-die MC is more like a Northbridge.


RE: CSI/Hypertransport?
By Trisped on 6/14/2006 2:30:29 PM , Rating: 2
No, it is a memory controller. It provides an interface between the CPU and the main system memory. Through an unrelated interface (HT) the CPU access the North Bridge which controls the rest of the hard ware. The North Bridge directly controls the PCIe, interfaces with the SB, and does a few other things, depending on the design.

[b]All motherboards have a north bridge[/b] to connect the CPU to the rest of the system.


RE: CSI/Hypertransport?
By Viditor on 6/15/2006 10:57:17 PM , Rating: 2
The only common function of an NB has been as an interface from the CPU to the Main Memory. This is why the speed of the bus to the NB is called the FSB. The South Bridge has always been the center for all of the other communications (with the exception of AGP).
The PCIe devices (for Intel) hang off both the NB and the SB.
http://www.webconnexxion.com/raid/info_pages.php?p...
For AMD systems, the NB is on the die and there is a single chip solution in the form of the MCP, though there are still some chipsets (Via) that prefer to split things up so that they can use their propietary VLink connections rather than HT.


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