AMD Announces "Torrenza" Technology
June 1, 2006 2:20 PM
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AMD's "Torrenza" platform mock up
AMD opens up the Opteron architecture to other microprocessor R&D companies
Today AMD unveiled what it calls the evolution of enterprise level computing, called
. The new platform, says AMD, will utilize next-generation multi-core 64-bit processor that have the capability to work alongside specialized co-processors.
previously reported that AMD was considering working with
co-processing design firms such as ClearSpeed
, to develop and design platforms that would be able to utilize specialized processors for specific duties alongside the general host processor in a traditional Opteron socket.
, AMD has designed what it calls an open architecture, based on the next wave of Opteron processors, which allow what AMD calls "Accelerators." Using the add-in accelerators, a system will be capable of peforming specialized calculations similar in fashion to the way we use GPUs today.
Because of its flexibility, the HyperTransport protocol allows a multitude of co-processor designs that are already compatible with systems on other platforms. For example, with
, specialized co-processors are able to sit directly into an Opteron socket, and communicate directly with the entire system. During the conference, Cray Inc. noted that it had worked with AMD to design a system where a system can contain even up to three different co-processors, all dedicated to specialized tasks. All three processors would communicate directly with Opteron processors and the system chipset harmonously. The open-ended nature of
will allow companies to design specialized processors to plug-in and work with
-enabled Opteron systems. Although AMD acknowledges many of these applications can run off PCIe and other connection technologies,
emphasizes HT-3 and HTX in particular.
AMD representatives said that because of the archicture,
allows very low latency communication between chipset, main processor and co-processors. According to both Cray and AMD, applications can be written in a way where all the variouis processing architectures are recognized and are fully usable.
-aware applications are on the way said Cray, but the company did admit that developing them was very much "rocket-science".
This article is over a month old, voting and posting comments is disabled
6/1/2006 8:39:37 PM
"Because of its flexibility, the HyperTransport protocol allows a multitude of designs that are now capable with systems from Intel. "
Sorry this sentence totally lost me!
Did you mean to say AMD rather than Intel ? Intel don't do hypertransport.
Did you mean compatible rather than "capable with" ?
PLEASE CLARIFY what you mean because it makes no sense to me.
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