AMD Announces More K8L Details
June 1, 2006 2:02 PM
comment(s) - last by
AMD's K8L diagram
AMD's K8L cache design
Four 16-bit or Eight 8-bit HyperTransport Links
K8L's instruction dispatch diagram
K8L details continue to pour in at AMD's Technology Analyst Day
During the AMD Technology Analyst Day, AMD’s CTO Phil Hester rehashed the majority of the
K8L information we discussed on
several days ago
, but disclosed further details on specifics. Hester was very specific to refer to these new technologies as simply “new architecture,” and never using the K8L core name.
Internally, AMD engineers use the codename
to describe the "new architecture."
A major push for AMD’s K8L design is in “modular” component design – meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs. To some extent, processor design is already modular with libraries and designs that are developed individually. However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing “better define the interfaces for each of these building blocks.”
Additionally, Hester revealed some more information about the cache specifics on K8L. Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache. The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap. One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.
A major feature of K8L is DICE, or Dynamic Independent Core Engagement. Essentially, the ACPI layer will have the ability to dynamically adjust individual cores and crossbars on the processor. Each processor core will have the ability to enter its own power-state, or p-state, allowing a K8L processor the ability to conserve power when the system does not have enough threads to utilize the other processor cores. Intel’s Core processors have the ability to enter c-states on a per-core basis, but the AMD demonstration showed a quad-core K8L processor dip individual cores into full halt.
Opteron servers right now are, for the most part, limited to PCs with eight sockets or less. Part of this is due to the fact that each processor has only three HyperTransport links. Hester announced that the next generation Opteron core will have four 16-bit HyperTransport-3 links running at 2.6GHz each. These four links can reconfigure into eight 8-bit HyperTransport links in a process called “un-ganging,” which is
a fundamental feature of HyperTransport-3
. Essentially, one could have an eight-socket server with thirty-two fully connected cores. Each processor will be able to take advantage of any of the eight memory banks within one memory hop. The HyperTransport-3 specification claims un-ganging mode can work on the fly, meaning that even a fully connected eight-socket server could dynamically change two 8-bit links into a single 16-bit link during operation to increase I/O at critical moments.
K8L is designed as a native quad-core design, although slides from the Technology Analyst Day also revealed that a dual-core desktop SKU will appear in mid-2007. So far,
has touched a little bit on the
65nm quad-core code names
announced in AMD roadmaps, but to our knowledge the code names for dual-core K8L processors have not been disclosed.
Please read the
update to this article about the K8L L1 cache sizes
This article is over a month old, voting and posting comments is disabled
6/2/2006 9:16:33 AM
"AMD's K8L die-shot and main points"
That doesn't look like a die shot to me. More like a screen shot of the processor layout.
A die shot would indicate that it was a picture taken of actual silicon.
"We don't know how to make a $500 computer that's not a piece of junk." -- Apple CEO Steve Jobs
Recent AMD Retractions
July 6, 2006, 1:25 PM
Gearing Up For AMD Revision G
May 24, 2006, 5:35 AM
AMD K8L: Quad Core Desktops And So Much More
May 18, 2006, 2:37 AM
HyperTransport 3.0 Ratified Today
April 24, 2006, 12:45 PM
3/7/2014 Daily Hardware Reviews
March 7, 2014, 10:19 AM
Quick Note: OCZ Z-Drive 4500 PCIe SSD Gets Official
March 4, 2014, 9:53 AM
3/4/2014 Daily Hardware Reviews
March 4, 2014, 8:45 AM
2/27/2014 Daily Hardware Reviews
February 27, 2014, 11:54 AM
2/26/2014 Daily Hardware Reviews
February 26, 2014, 10:28 AM
AVADirect Unleashes High-End Supermicro, Tyan GPU Servers
February 7, 2014, 12:35 PM
Most Popular Articles
Bitcoin King Pt. II: Mt. Gox's Dictator Karpelès Proves Tragically Flawed
March 7, 2014, 1:12 PM
Hack Reveals Fallen Bitcoin CEO's Posh Tokyo Penthouse
March 10, 2014, 4:28 PM
Tesla Motors Calls New Jersey Out on New Rule Against Its Direct Sales Model
March 11, 2014, 12:01 PM
NASA Considering SpaceX "Red Dragon" for Returning Mars Samples to Earth
March 10, 2014, 2:43 PM
India Could Rock Google With Its Biggest Antitrust Fine Yet -- $5B USD
March 10, 2014, 8:12 PM
Latest Blog Posts
Tesla vs. BMW: Who Has the Safer EV?
Feb 1, 2014, 2:56 PM
Justice Leaks Details of Next HTC One Two Flagship Phone
Dec 5, 2013, 4:04 PM
Global Cyber Espionage Concerns Reveal Growing Cyber Armies
Nov 29, 2013, 11:04 AM
Is The Period Becoming an Expression of Anger?
Nov 26, 2013, 2:02 PM
NSA and Congress -- You Will Never Kill the Constitution, It's an Idea
Nov 10, 2013, 2:00 PM
More Blog Posts
Copyright 2014 DailyTech LLC. -
Terms, Conditions & Privacy Information