DailyTech - AMD Announces More K8L Details

Submit News

Hardware AMD Announces More K8L Details
Kristopher Kubicki (Blog) - June 1, 2006 2:02 PM

55 comment(s) - last by Regs.. on Jun 8 at 9:33 AM

AMD's K8L diagram

AMD's K8L cache design

Four 16-bit or Eight 8-bit HyperTransport Links

K8L's instruction dispatch diagram

K8L details continue to pour in at AMD's Technology Analyst Day

During the AMD Technology Analyst Day, AMD’s CTO Phil Hester rehashed the majority of the K8L information we discussed on DailyTech several days ago, but disclosed further details on specifics. Hester was very specific to refer to these new technologies as simply “new architecture,” and never using the K8L core name.

Internally, AMD engineers use the codename Greyhound to describe the "new architecture."

A major push for AMD’s K8L design is in “modular” component design – meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs. To some extent, processor design is already modular with libraries and designs that are developed individually. However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing “better define the interfaces for each of these building blocks.”

Additionally, Hester revealed some more information about the cache specifics on K8L. Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache. The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap. One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.

A major feature of K8L is DICE, or Dynamic Independent Core Engagement. Essentially, the ACPI layer will have the ability to dynamically adjust individual cores and crossbars on the processor. Each processor core will have the ability to enter its own power-state, or p-state, allowing a K8L processor the ability to conserve power when the system does not have enough threads to utilize the other processor cores. Intel’s Core processors have the ability to enter c-states on a per-core basis, but the AMD demonstration showed a quad-core K8L processor dip individual cores into full halt.

Opteron servers right now are, for the most part, limited to PCs with eight sockets or less. Part of this is due to the fact that each processor has only three HyperTransport links. Hester announced that the next generation Opteron core will have four 16-bit HyperTransport-3 links running at 2.6GHz each. These four links can reconfigure into eight 8-bit HyperTransport links in a process called “un-ganging,” which is a fundamental feature of HyperTransport-3. Essentially, one could have an eight-socket server with thirty-two fully connected cores. Each processor will be able to take advantage of any of the eight memory banks within one memory hop. The HyperTransport-3 specification claims un-ganging mode can work on the fly, meaning that even a fully connected eight-socket server could dynamically change two 8-bit links into a single 16-bit link during operation to increase I/O at critical moments.

K8L is designed as a native quad-core design, although slides from the Technology Analyst Day also revealed that a dual-core desktop SKU will appear in mid-2007. So far, DailyTech has touched a little bit on the 65nm quad-core code names announced in AMD roadmaps, but to our knowledge the code names for dual-core K8L processors have not been disclosed.

Update 07/06/2006: Please read the update to this article about the K8L L1 cache sizes.

Comments

Threshold

Username
Password
remember me

This article is over a month old, voting and posting comments is disabled

RE: 1207

By saratoga on 6/1/2006 9:07:53 PM , Rating: 2

quote:
It just doesn't add up. To add DDR2 support to the present socket 939 based Athlons, it took one pin.

It took a lot more then that, just S939 had tons of unused pins for some reason. IIRC it only used something like 700 of them, the rest weren't connected.

Anyway 1207 might be forwards compatable with HT3 or FBDIMMs, which would use up a LOT of extra pins. Or it could just have a lot of useless pins, like 939.

Parent

cache

By hwhacker on 6/1/2006 9:35:56 PM , Rating: 2

Background info for impending question:

Ok, so initial K8L's will have 2mb L3. AMD has said that they plan to increase it. The Z-ram rumours that were flying something-fierce proposed AMD planned to inbed 5mb Z-ram on their processors. While Greyhound for the desktop socket (let's call it) "AM3" seems to be the first processors for it's sector using K8L tech, Cadiz is also on the roadmap with the same main specs, only in the higher-end "workstation" sector. This section is that which includes desktop Opterons, something notibley currently absent from the AM2 platform.

Here's my questions are this:

Will the initial K8L's have Z-ram for L3, or will be it SRAM with perhaps a transition to Z-RAM? Perhaps the kicker question is...Is Cadiz planned to have the rumoured 5mb of L3 cache, perhaps used in high-end "AM3" products such as later FX's and/or desktop Opterons? That would be sweet.

Anyone...Kris...Bueler? ;)
TIA.

Parent

RE: cache

By SocketF on 6/2/2006 6:36:30 AM , Rating: 2

quote:
Will the initial K8L's have Z-ram for L3, or will be it SRAM with perhaps a transition to Z-RAM?

If you look at the K8L Die photo, together with the information that it is ~2 MB L3, then it must be normal S-RAM, because the L3 area is to big for being 2 MB L3 with Z-RAM.
It might be possible to use the same area for Z-RAM(if it can keep up the same timings), but then it would be around 10 MB L3, as Z-RAM is 5 times denser than S-RAM ;-)

cheers

SocketF

Parent

RE: 1207

By Tyler 86 on 6/2/2006 3:41:35 AM , Rating: 2

The first poster hinted at it, but yes, it's Socket F, for "Fishy". Please, continue speculation. Hrm.

After all, more pins must mean more something, right? ...
Maybe they make the chip look prettier, ala S939?

Here's hoping they use the god forsaken things.

Parent

"A lot of people pay zero for the cellphone ... That's what it's worth." -- Apple Chief Operating Officer Timothy Cook