AMD Announces More K8L Details
June 1, 2006 2:02 PM
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AMD's K8L diagram
AMD's K8L cache design
Four 16-bit or Eight 8-bit HyperTransport Links
K8L's instruction dispatch diagram
K8L details continue to pour in at AMD's Technology Analyst Day
During the AMD Technology Analyst Day, AMD’s CTO Phil Hester rehashed the majority of the
K8L information we discussed on
several days ago
, but disclosed further details on specifics. Hester was very specific to refer to these new technologies as simply “new architecture,” and never using the K8L core name.
Internally, AMD engineers use the codename
to describe the "new architecture."
A major push for AMD’s K8L design is in “modular” component design – meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs. To some extent, processor design is already modular with libraries and designs that are developed individually. However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing “better define the interfaces for each of these building blocks.”
Additionally, Hester revealed some more information about the cache specifics on K8L. Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache. The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap. One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.
A major feature of K8L is DICE, or Dynamic Independent Core Engagement. Essentially, the ACPI layer will have the ability to dynamically adjust individual cores and crossbars on the processor. Each processor core will have the ability to enter its own power-state, or p-state, allowing a K8L processor the ability to conserve power when the system does not have enough threads to utilize the other processor cores. Intel’s Core processors have the ability to enter c-states on a per-core basis, but the AMD demonstration showed a quad-core K8L processor dip individual cores into full halt.
Opteron servers right now are, for the most part, limited to PCs with eight sockets or less. Part of this is due to the fact that each processor has only three HyperTransport links. Hester announced that the next generation Opteron core will have four 16-bit HyperTransport-3 links running at 2.6GHz each. These four links can reconfigure into eight 8-bit HyperTransport links in a process called “un-ganging,” which is
a fundamental feature of HyperTransport-3
. Essentially, one could have an eight-socket server with thirty-two fully connected cores. Each processor will be able to take advantage of any of the eight memory banks within one memory hop. The HyperTransport-3 specification claims un-ganging mode can work on the fly, meaning that even a fully connected eight-socket server could dynamically change two 8-bit links into a single 16-bit link during operation to increase I/O at critical moments.
K8L is designed as a native quad-core design, although slides from the Technology Analyst Day also revealed that a dual-core desktop SKU will appear in mid-2007. So far,
has touched a little bit on the
65nm quad-core code names
announced in AMD roadmaps, but to our knowledge the code names for dual-core K8L processors have not been disclosed.
Please read the
update to this article about the K8L L1 cache sizes
This article is over a month old, voting and posting comments is disabled
RE: L1 Cache
6/1/2006 4:49:37 PM
I guess with quad core they cut back all the cache to free up die space. Thats a shame.
But then again, maybe they have compensated with a better front end on that thing.
RE: L1 Cache
6/1/2006 5:10:58 PM
128k was really large for an L1. It was designed for the days when L2 caches were offdie, not for modern on die L2 (and now L3!), so it was probably outdated.
A smaller L1 allows for faster access, wider data path, and/or better associativity for a given die size.
RE: L1 Cache
6/1/2006 7:01:17 PM
lower L1 cache means BETTER cache latency
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