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AMD's K8L diagram

AMD's K8L cache design

Four 16-bit or Eight 8-bit HyperTransport Links

K8L's instruction dispatch diagram
K8L details continue to pour in at AMD's Technology Analyst Day

During the AMD Technology Analyst Day, AMD’s CTO Phil Hester rehashed the majority of the K8L information we discussed on DailyTech several days ago, but disclosed further details on specifics.  Hester was very specific to refer to these new technologies as simply “new architecture,” and never using the K8L core name. 

Internally, AMD engineers use the codename Greyhound to describe the "new architecture."

A major push for AMD’s K8L design is in “modular” component design – meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs.  To some extent, processor design is already modular with libraries and designs that are developed individually.  However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing “better define the interfaces for each of these building blocks.”

Additionally, Hester revealed some more information about the cache specifics on K8L.  Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache.  The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap.  One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB.  AMD employees have assured us this move is logical with the addition of L3 cache. 

A major feature of K8L is DICE, or Dynamic Independent Core Engagement.  Essentially, the ACPI layer will have the ability to dynamically adjust individual cores and crossbars on the processor.   Each processor core will have the ability to enter its own power-state, or p-state, allowing a K8L processor the ability to conserve power when the system does not have enough threads to utilize the other processor cores.  Intel’s Core processors have the ability to enter c-states on a per-core basis, but the AMD demonstration showed a quad-core K8L processor dip individual cores into full halt.

Opteron servers right now are, for the most part, limited to PCs with eight sockets or less.  Part of this is due to the fact that each processor has only three HyperTransport links.  Hester announced that the next generation Opteron core will have four 16-bit HyperTransport-3 links running at 2.6GHz each.  These four links can reconfigure into eight 8-bit HyperTransport links in a process called “un-ganging,” which is a fundamental feature of HyperTransport-3.  Essentially, one could have an eight-socket server with thirty-two fully connected cores.  Each processor will be able to take advantage of any of the eight memory banks within one memory hop.  The HyperTransport-3 specification claims un-ganging mode can work on the fly, meaning that even a fully connected eight-socket server could dynamically change two 8-bit links into a single 16-bit link during operation to increase I/O at critical moments. 

K8L is designed as a native quad-core design, although slides from the Technology Analyst Day also revealed that a dual-core desktop SKU will appear in mid-2007.  So far, DailyTech has touched a little bit on the 65nm quad-core code names announced in AMD roadmaps, but to our knowledge the code names for dual-core K8L processors have not been disclosed.

Update 07/06/2006:
  Please read the update to this article about the K8L L1 cache sizes.

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As predicted
By mushi799 on 6/1/2006 3:11:55 PM , Rating: 2
AMD releases an annoucement a month or so before Intel releases their next cpu cores.

This annoucement was design to make some ppl wait. After reading these comments, it probably worked.

RE: As predicted
By TomZ on 6/1/2006 3:15:43 PM , Rating: 2
AMD fans will always wait for AMD, regardless of what Intel is doing.

RE: As predicted
By proamerica on 6/1/2006 3:35:47 PM , Rating: 2
"Good things come to those who wait."

RE: As predicted
By PT2006 on 6/1/2006 3:42:09 PM , Rating: 1
Like AM2 right?

RE: As predicted
By peternelson on 6/1/2006 5:15:27 PM , Rating: 1
Yes, like AM2 "4x4" dual sockets of dualcore goodness ;-)

RE: As predicted
By Fenixgoon on 6/1/2006 7:04:48 PM , Rating: 2
it's no different than waiting for conroe over AM2.. now you can wait for K8L over conroe over AM2 :P

regardless, i think both K8L and conroe will absolutely rock, which means we win as consumers :)

RE: As predicted
By Torched on 6/2/2006 12:37:06 PM , Rating: 2
Like AM2 right?

AM2 is not an architecture, its an interface. What you mean to say is Rev. F. The processor discussed in this article is Rev. G and uses the Socket F interface.

RE: As predicted
By KristopherKubicki on 6/2/2006 4:32:10 PM , Rating: 2
K8L is something after Revision G, which several websites are already starting to call Revision H. Revision G is for the most part a 65nm SOI revision F chip.

RE: As predicted
By mlittl3 on 6/1/2006 4:07:26 PM , Rating: 2
This is not about AMD fans. This is not about gamers sitting in their moms basements trying to get a few more fps on Doom3. This is not about showing longer bars on bar graphs at hardware review sites. These things might seem important to those of us who buy a new desktop every 6 months and we only have to worry about supporting that one desktop.

This "new architecture" or whatever you want to call it is about multi-million dollar datacenters, genomic computation clusters, physical chemistry computation centers, etc. These kinds of people need well designed CPUs to handle tasks ranging from mapping the human genome to managing huge databases for financial institutions. They only upgrade when funds allow and they require strict, strict validation of the hardware. These kinds of things take years sometimes.

So leave your mom's basement. Walk down to your local bank and ask them are they an AMD or Intel fanboi or are they interested in extremely stable, high IPC server/workstation platforms that are future proof.

RE: As predicted
By Spoelie on 6/1/2006 4:26:21 PM , Rating: 2
IPC implies instruction per clockcycle, think that the final performance is a bit more important than what it can do in 1 clockcycle.

RE: As predicted
By Griswold on 6/1/2006 4:40:40 PM , Rating: 4
You mean like Intel benchmarking a product 6 months before it hits the streets versus a technology that has been on the market for (lets be generous and only talk about dual cores here) 10 months?

You sure sound like somebody who feels like AMD will rain on your parade next year. Then again, this is mainly server stuff.. does that really matter to you?

"You can bet that Sony built a long-term business plan about being successful in Japan and that business plan is crumbling." -- Peter Moore, 24 hours before his Microsoft resignation
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