Print 55 comment(s) - last by Regs.. on Jun 8 at 9:33 AM

AMD's K8L diagram

AMD's K8L cache design

Four 16-bit or Eight 8-bit HyperTransport Links

K8L's instruction dispatch diagram
K8L details continue to pour in at AMD's Technology Analyst Day

During the AMD Technology Analyst Day, AMD’s CTO Phil Hester rehashed the majority of the K8L information we discussed on DailyTech several days ago, but disclosed further details on specifics.  Hester was very specific to refer to these new technologies as simply “new architecture,” and never using the K8L core name. 

Internally, AMD engineers use the codename Greyhound to describe the "new architecture."

A major push for AMD’s K8L design is in “modular” component design – meaning everything from L3 cache to memory controllers are developed as individual components and linked together with reusable, robust designs.  To some extent, processor design is already modular with libraries and designs that are developed individually.  However, Hester insists this new modular approach takes this modular approach even further, claiming that the company is developing “better define the interfaces for each of these building blocks.”

Additionally, Hester revealed some more information about the cache specifics on K8L.  Each K8L core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2 cache.  The base models of K8L will have 2MB of shared L3 cache, but Hester also went on to claim that adding more L3 cache was in the company’s roadmap.  One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB.  AMD employees have assured us this move is logical with the addition of L3 cache. 

A major feature of K8L is DICE, or Dynamic Independent Core Engagement.  Essentially, the ACPI layer will have the ability to dynamically adjust individual cores and crossbars on the processor.   Each processor core will have the ability to enter its own power-state, or p-state, allowing a K8L processor the ability to conserve power when the system does not have enough threads to utilize the other processor cores.  Intel’s Core processors have the ability to enter c-states on a per-core basis, but the AMD demonstration showed a quad-core K8L processor dip individual cores into full halt.

Opteron servers right now are, for the most part, limited to PCs with eight sockets or less.  Part of this is due to the fact that each processor has only three HyperTransport links.  Hester announced that the next generation Opteron core will have four 16-bit HyperTransport-3 links running at 2.6GHz each.  These four links can reconfigure into eight 8-bit HyperTransport links in a process called “un-ganging,” which is a fundamental feature of HyperTransport-3.  Essentially, one could have an eight-socket server with thirty-two fully connected cores.  Each processor will be able to take advantage of any of the eight memory banks within one memory hop.  The HyperTransport-3 specification claims un-ganging mode can work on the fly, meaning that even a fully connected eight-socket server could dynamically change two 8-bit links into a single 16-bit link during operation to increase I/O at critical moments. 

K8L is designed as a native quad-core design, although slides from the Technology Analyst Day also revealed that a dual-core desktop SKU will appear in mid-2007.  So far, DailyTech has touched a little bit on the 65nm quad-core code names announced in AMD roadmaps, but to our knowledge the code names for dual-core K8L processors have not been disclosed.

Update 07/06/2006:
  Please read the update to this article about the K8L L1 cache sizes.

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RE: Bright future
By mountcarlmore on 6/1/2006 3:09:21 PM , Rating: 2
you can say that the k8 is k7 on steroids, you can say conroe is the p6 on steroids. If you expect a company to just outright change every single part of the microprocessor, thats not very realistic with the time frames theyre working with.

RE: Bright future
By Griswold on 6/1/2006 4:35:50 PM , Rating: 2
Well yes I agree with you to some extend. But I still dont think calling this a new architecture is really the right thing to do. The changes from K7 to K8 were bigger. IMC, AMD64, HTT to name a few.

K8L on the other hand, seems to mostly make existing things "fatter and wider". Granted, L3 is a new.

Anyway, if it delivers, who cares what its called.

RE: Bright future
By saratoga on 6/1/2006 5:15:57 PM , Rating: 2
The changes from K7 to K8 were bigger. IMC, AMD64, HTT to name a few.

ISA changes are not really arch. Though the address space and int changes were.

But anyway, the K8L will have a new HT and IMC design, not to mention ISA extensions anyway, so thats not really a valid example.

Furthermore, K7 to K8 was mostly just front end changes. AMD left the K7 backend mostly untouched (aside from the wider ALU and other x86-64 changes). The K8L will have upgraded front end (all 3 levels of cache redesigned, IF upgraded, more aggressive OOOE) and backend parts (massively improved execution resources). IMO this is at least as big a change as the K8. Possibly a much larger one, though the details still aren't clear.

RE: Bright future
By Regs on 6/8/2006 9:33:38 AM , Rating: 2

The changes from K7 to K8 were bigger. IMC, AMD64, HTT to name a few.

Bigger yes, but IPC was just not there. Hopefully the K8L will solve this with lower latency in it's L2 cache and a smarter, more accurate prefetch. I have no idea what they did to the core itself yet as it's not as easy to assume and squeeze information about the registry units.

RE: Bright future
By Garreye on 6/1/2006 7:10:08 PM , Rating: 2
it is being called K8L and not K9, so that is a reflection of the idea of K8 on steroids....

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