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AMD "Orleans" Die Shot
Before there was K8L, there was Rev G

AMD has brought us Revision F and talked a bit about K8L, but what of the processor gap between AM2 and K8L?  AMD's intermediate 65nm SOI stepping stone is Revision G.  The company has taken substantial steps over the last few months to convert Fab 36 to 65nm SOI production, and the company has also announced that Chartered Semiconductor will act as spillover production for 65nm CPUs. Soon, AMD will start putting these resources to use with the second generation DDR2 CPUs.

The transition from AMD's Revision D K8 processors to Revision E K8 was essentially the transition from 130nm die process to 90nm SOI with the addition of SSE3.  The progression Revision E to F was then only the addition of DDR2 memory support to the K8 memory controller, as well as the integration of Pacifica virtual technology.  Processor revisions, for AMD, come in very small, focused increments -- and the next one for the company is the shift from 90nm SOI to 65nm SOI.  Like the progression from Revision D to Revision E, Revision F to Revision G will not require any socket changes. 
 
AMD's first desktop Revision G core, Brisbane, showed up on AMD's roadmaps just a few weeks agoBrisbane, like Windsor, does not have two separate core distinctions for half-cache processors like with Toledo/Manchester.  This processor family will come in two varieties; one with 2x1MB L2 cache and one with 2x512KB L2 cache.

AMD 65nm Desktop Processor Roadmap 2006
Processor
Socket
Frequency
L2 Cache
Launch Date
Athlon 64 4800+
AM2
2.4GHz
2x1MB
12/06
Athlon 64 4600+
AM2
2.4GHz
2x512KB
12/06
Athlon 64 4400+
AM2
2.2GHz
2x1MB
12/06
Athlon 64 4200+
AM2
2.2GHz
2x512KB
12/06

Brisbane
is a massively ambitious core.  The Revision E Socket 939 platform consisted of San Diego, two versions of Toledo, Venus, Denmark and Venice.  Yesterday AMD announced the Windsor dual-core and Orleans single-core desktop processors with the Santa Ana dual-core processor on the way.  When Brisbane is announced later this year, all of these processor families will effectively take the backseat to Brisbane cores. 

AMD has not announced other Revision G processors specifics yet, although 65nm Sempron processors, dubbed Sparta, will replace 90nm SOI Manila processors that were just announced yesterday.  Do not expect a simultaneous launch of Sparta and Brisbane, as the Brisbane components that are expected to ship this December are low volume productions.

Revision G is not limited to just the desktop either.  Tyler and Sherman are AMD's upcoming Revision G 65nm SOI successors to the recently announced Taylor and Keene Socket S1 DDR2 Turions and Semprons.  AMD's roadmaps have revealed that there will not be a 65nm successor to Trinidad nor Richmond, as the Energy Efficient Sparta and Brisbane processors will more or less fill the gap between Turion and Athlon/Sempron processors for DTR notebooks. These Revision G processors will not receive a HyperTransport frequency bump.

AMD has been hesitant to list TDP information for Brisbane, although AMD's most recent partner roadmap reveals that Tyler and Sherman will have the same TDP envelopes as Taylor and Keene; 35W and 25W respectively.

Deerhound, the Revision G successor to Santa Rosa and Santa Ana, is the only server core on the long-term AMD roadmaps.  AMD will reduce all six 90nm Opteron cores into just two with the Santa Rosa and Santa Ana -- Santa Rosa will be the unified Socket F dual-core Opteron while Santa Ana will become the Socket AM2 dual-core Opteron specifically for 1U servers and high end workstations. With Revision G, AMD goes one step further with four cores on the Deerhound, though the features on Deerhound are virtually identical to Santa Rosa with the exception of the die shrink.  K8L processors will then replace Deerhound in 2008.



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RE: Processor revisons
By Furen on 5/24/2006 12:03:36 PM , Rating: 3
The reason why the IMC only supports integer dividers is because having a non-integer divider will make the memory run out of sync with the memory controller. Just think about it, if you run on a 6.5 mem divider do you have to skip six and a HALF clocks? Kind of hard to tell the CPU to talk to the ram in between clocks.

Also, remember that these chips are not even close to bandwidth starved so down-clocking the DRAM slightly does not result in a significant performance decrease.


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