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AMD "Orleans" Die Shot
Before there was K8L, there was Rev G

AMD has brought us Revision F and talked a bit about K8L, but what of the processor gap between AM2 and K8L?  AMD's intermediate 65nm SOI stepping stone is Revision G.  The company has taken substantial steps over the last few months to convert Fab 36 to 65nm SOI production, and the company has also announced that Chartered Semiconductor will act as spillover production for 65nm CPUs. Soon, AMD will start putting these resources to use with the second generation DDR2 CPUs.

The transition from AMD's Revision D K8 processors to Revision E K8 was essentially the transition from 130nm die process to 90nm SOI with the addition of SSE3.  The progression Revision E to F was then only the addition of DDR2 memory support to the K8 memory controller, as well as the integration of Pacifica virtual technology.  Processor revisions, for AMD, come in very small, focused increments -- and the next one for the company is the shift from 90nm SOI to 65nm SOI.  Like the progression from Revision D to Revision E, Revision F to Revision G will not require any socket changes. 
AMD's first desktop Revision G core, Brisbane, showed up on AMD's roadmaps just a few weeks agoBrisbane, like Windsor, does not have two separate core distinctions for half-cache processors like with Toledo/Manchester.  This processor family will come in two varieties; one with 2x1MB L2 cache and one with 2x512KB L2 cache.

AMD 65nm Desktop Processor Roadmap 2006
L2 Cache
Launch Date
Athlon 64 4800+
Athlon 64 4600+
Athlon 64 4400+
Athlon 64 4200+

is a massively ambitious core.  The Revision E Socket 939 platform consisted of San Diego, two versions of Toledo, Venus, Denmark and Venice.  Yesterday AMD announced the Windsor dual-core and Orleans single-core desktop processors with the Santa Ana dual-core processor on the way.  When Brisbane is announced later this year, all of these processor families will effectively take the backseat to Brisbane cores. 

AMD has not announced other Revision G processors specifics yet, although 65nm Sempron processors, dubbed Sparta, will replace 90nm SOI Manila processors that were just announced yesterday.  Do not expect a simultaneous launch of Sparta and Brisbane, as the Brisbane components that are expected to ship this December are low volume productions.

Revision G is not limited to just the desktop either.  Tyler and Sherman are AMD's upcoming Revision G 65nm SOI successors to the recently announced Taylor and Keene Socket S1 DDR2 Turions and Semprons.  AMD's roadmaps have revealed that there will not be a 65nm successor to Trinidad nor Richmond, as the Energy Efficient Sparta and Brisbane processors will more or less fill the gap between Turion and Athlon/Sempron processors for DTR notebooks. These Revision G processors will not receive a HyperTransport frequency bump.

AMD has been hesitant to list TDP information for Brisbane, although AMD's most recent partner roadmap reveals that Tyler and Sherman will have the same TDP envelopes as Taylor and Keene; 35W and 25W respectively.

Deerhound, the Revision G successor to Santa Rosa and Santa Ana, is the only server core on the long-term AMD roadmaps.  AMD will reduce all six 90nm Opteron cores into just two with the Santa Rosa and Santa Ana -- Santa Rosa will be the unified Socket F dual-core Opteron while Santa Ana will become the Socket AM2 dual-core Opteron specifically for 1U servers and high end workstations. With Revision G, AMD goes one step further with four cores on the Deerhound, though the features on Deerhound are virtually identical to Santa Rosa with the exception of the die shrink.  K8L processors will then replace Deerhound in 2008.

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Ace up their sleeve?
By Stele on 5/24/2006 6:59:14 AM , Rating: 4
Anand closed his AM2 review on Anandtech by hinting that AMD still had one more trick up their sleeve before the year's out. I wonder if this is it. As always, eagerly looking forward to launch and benchmarks :P

65nm will probably bring about the usual benefits with respect to heat dissipation/TDP, overall power consumption, overclockability and yield (once the the fab ramps up).

RE: Ace up their sleeve?
By KristopherKubicki on 5/24/2006 7:03:58 AM , Rating: 2
I haven't talked to Anand in a while, but I'm pretty sure the trick he is referring to is Brisbane. At least, that's all i see on the roadmaps.

RE: Ace up their sleeve?
By Zoomer on 5/24/2006 7:28:52 AM , Rating: 1
12/06 ?

Will we really see it in june? Thought it wasn't due till the end of the year.

RE: Ace up their sleeve?
By Xavian on 5/24/2006 7:37:42 AM , Rating: 2
December 06 not 12th June 06 :p

Brisbane certainly seems interesting.

RE: Ace up their sleeve?
By George Powell on 5/25/2006 3:28:42 AM , Rating: 2
International date standards are poor.

Depending on how you read 12/06 it could mean:

December 2006, 6th December, 12th June.

I would much rather the use of letters to designate month and the number before being the day and the number after being the year. It would just 'make sense'

RE: Ace up their sleeve?
By xdrol on 5/28/2006 11:22:44 AM , Rating: 2
There are no real date standards, everyone writes theese numbers in order of his/her own taste :)

For me, your way does not make any sense, because the most "important" part of a date is the year, so it should come first, the second is the month, third is the day.

But if all just wrote month with letters, and years with 4 digits, there would be no more confusion.

RE: Ace up their sleeve?
By Soviet Robot on 5/29/2006 12:05:21 AM , Rating: 2
Just stick to abbreviations for months.

RE: Ace up their sleeve?
By wdomburg on 7/17/2006 11:24:21 PM , Rating: 2
ISO 8601. Learn it, live it, love it. :)

RE: Ace up their sleeve?
By Viditor on 5/24/2006 8:23:01 AM , Rating: 2
But what about "Bulldozer"?
And what is the name for K8L Dual core (and when is it being released)?

All I have been able to find so far is Charlie D's stuff at the Inq...

RE: Ace up their sleeve?
By defter on 5/24/06, Rating: 0
RE: Ace up their sleeve?
By ktgktg on 5/24/2006 9:01:32 AM , Rating: 2
I think Anand was talking about the new Opterons, which "won't affect the majority of people" and is "high end".

BTW, last time I checked revision D was the first 90 nm, not E. Winchester, Oakville, remember?

RE: Ace up their sleeve?
By dgingeri on 5/24/2006 11:09:01 AM , Rating: 2
I think Anand was talking about the new Opterons, which "won't affect the majority of people" and is "high end".

BTW, last time I checked revision D was the first 90 nm, not E. Winchester, Oakville, remember?

Winchester was E1, not D. the ones we now know and love on socket 939, Toledo, San Diego, etc., are E4-E6. I think D series was just an updated Newcastle, but I don't remember for sure.

RE: Ace up their sleeve?
By Spoelie on 5/24/2006 11:17:34 AM , Rating: 2
A hammer, B newcastle, C solved mem controller issues, D winchester (really, check cpuid screenshots around the web), E were the venice type processor, with E6 adding new mem dividers for faster DDR. I have a venice with E3 stepping and one with E6. The later is also the better TDP, checkable by tcasemax

RE: Ace up their sleeve?
By Jeeves on 5/24/2006 12:41:23 PM , Rating: 3
Actually, an A-Stepping never made it to retail, IIRC. The B-Stepping were the earliest Opterons (and Sledgehammers), C0 Clawhammers, CG Clawhammers and Newcastles, D0 Winchester and E3/E6 Venice ...

BTW, did AMD rename their processors? Should be Athlon 64 X2 if it's Dual Core, right?

RE: Ace up their sleeve?
By Spoelie on 5/24/2006 5:15:18 PM , Rating: 2
you're right, I realised I had about everything before D wrong after posting but it's kinda hard to edit :)

By unparalleled intellect on 5/24/2006 11:14:13 AM , Rating: 2
When he says, high end, I would assume that he's talking about overclockers who have the equipment to pursue such ventures.

RE: Ace up their sleeve?
By Googer on 6/1/2006 1:59:08 AM , Rating: 2
Processor revisons
By Larry on 5/24/2006 7:34:13 AM , Rating: 3
If D to E shrank process and added SSE3 and E to F added DDR2 and Pacifica then can anyone think what the F to G might add other then the process shrink.
Certainly a process shrink will improve thermal numbers and lower voltage requirements, but in terms of code improvement I'm at a loss for what could be added at this point. Bringing HT3 in early would be nice though, but that's wishfull thinking I suspect. An improved divider clock for the memory controller to allow it to cleanly do the somewhat screwy memory frequencies that DDR2 has might also be nice.
Any guesses?


RE: Processor revisons
By mongoosesRawesome on 5/24/2006 8:15:06 AM , Rating: 2
Well, they could start adding some of the stuff that K8L will have. With the 65nm die shrink they should then have all the space they need. Its just a matter of how ambitious they are.

RE: Processor revisons
By Stele on 5/24/2006 8:22:56 AM , Rating: 2
Bringing HT3 in early would be nice though, but that's wishfull thinking I suspect

Well, one can hope! ;)

I second your opinion about the memory clock divider. Right now, AM2 CPUs with odd multiplier values are having trouble running DDR2-800 RAM at 800MHz because the memory divider only supports integer divisors - with the result that unless the CPU frequency can be divided by an integer to give 800, such CPUs would have to run the RAM at the closest possible frequency below 800. So far it seems that the only way around this is to allow fractional divisors, in particular .25 and .75 ... or just add fractionals in .25 increments (.25, .50, .75) or some such.

RE: Processor revisons
By Furen on 5/24/2006 12:03:36 PM , Rating: 3
The reason why the IMC only supports integer dividers is because having a non-integer divider will make the memory run out of sync with the memory controller. Just think about it, if you run on a 6.5 mem divider do you have to skip six and a HALF clocks? Kind of hard to tell the CPU to talk to the ram in between clocks.

Also, remember that these chips are not even close to bandwidth starved so down-clocking the DRAM slightly does not result in a significant performance decrease.

RE: Processor revisons
By Zoomer on 5/26/2006 6:05:55 AM , Rating: 2
The nice side effect of this is any any chip affected by this will be great if you want to domem divider 1:1 overclocking with valuerams! :p

RE: Processor revisons
By Spoelie on 5/24/2006 5:16:59 PM , Rating: 2
how would adding HT3 improve performance on the single socket performance side?

it wouldn't.

By Ecmaster76 on 5/24/2006 8:11:59 AM , Rating: 2
If that is the Rev G above, there is clearly a thir major structure.

L2 || L2
L2 || L2

I think it a L3 cache and perhaps even X Ram because I have never seen any feature of a die shot that looks quite like that before.

RE: L3
By Griswold on 5/24/2006 9:07:39 AM , Rating: 2
I think you mean Z-RAM? Anyway, shots that look like that have been on quite a few sheets from AMD and I've indeed been wondering what that part at the bottom with the text written over it is.

Another interesting thing in the upper part of the shot: the four bright square blocks in the middle. On older DIE shots, there are only 3 of them.

RE: L3
By Goty on 5/24/2006 9:22:13 AM , Rating: 1
HT Links? I dunno, how many links did the older X2s have between cores?

RE: L3
By Ecmaster76 on 5/24/2006 11:53:15 AM , Rating: 2
Oops, yeah i was still asleep. Another thing I just noticed is that the die shown is either single core or has an assymetrical core configuration. The elements on the left should mirror the ones on the right.

I know there has been talk about integrating a PCIe controller. However this probably wouldn't work with AM2, so unless AMD is going to be releasing single seated socket F mainboards, that is not it

RE: L3
By wretched on 5/25/2006 6:15:25 AM , Rating: 2
Whats interesting and puzzeling about the die photo above is there is no symmetry in the upper core section only in the L2 cache which is seen in single cores, the photo I dug up of older X2 die had two distinct mirror images of cores, and yet there does look like a L3 at bottom of this pic.

RE: L3
By wretched on 5/27/2006 7:51:57 PM , Rating: 2
If it is a L3 cache using Zram, with a 5 x density over sram, then my estimation on looking at surface area is 60 to 70% of the 2MB L2, which would be in the order of 6 to 7MB L3 cache

RE: L3
By jamannetje on 5/30/2006 5:32:33 AM , Rating: 3
It's a single-core die.

The text under the image says it is a shot of the Orleans core which is, according to the main text, a single-core Athlon.


What is Pacifica virtual technology
By electriple9 on 5/24/2006 2:57:00 PM , Rating: 2
Can someone explain what is Pacifica virtual technology

By TomZ on 5/24/2006 3:56:10 PM , Rating: 2
I don't mean to be rude, but you can pretty easily learn yourself:

RE: What is Pacifica virtual technology
By robber98 on 5/24/2006 4:20:57 PM , Rating: 2
Google is your friend ;)

AMD using Filipino terms :)
By Blackraven on 5/24/2006 10:55:10 PM , Rating: 1
Wow, I didn't AMD was using terms from the Tagalog dialect of the Filipino language.

Words/terms such as:
-90nm SOI Manila processors
- Santa Rosa will be the unified Socket F dual-core Opteron
- Santa Ana will become the Socket AM2 dual-core Opteron

Maybe they wanna a build a factory here in the Philippines (maybe to challenge Intel's processor plant in Cavite)

Ang masasabi ko lang sa AMD na sana maging mabuti ang negosyo sa industriya ng kompyuter :P

RE: AMD using Filipino terms :)
By Stele on 5/25/2006 2:22:03 AM , Rating: 3
Sorry to disappoint you, but it has nothing to do with using Tagalog per se. The recent AMD core codenames have mostly been named after places around the world or in the US.

Manila simply follows the pattern of major cities around the world - Venice, Brisbane and Sparta are others. Santa Ana and Santa Rosa are two cities in California, US. Besides, they are Spanish names (St. Anna/Anne and St. Rose), not Tagalog - only Manila is Tagalog.

RE: AMD using Filipino terms :)
By Maasracer on 5/25/2006 7:19:15 AM , Rating: 2

OT - Reminds me of my dad. Anytime he sees a SE Asian face on TV, he beams with pride and says, "That's a Filipino." On a few occasions, the name is flashed and it has like 40 letters usually indicating mainland SE Asia. WRONG!

How small can these chips get?
By Nocturnal on 5/25/2006 1:43:09 PM , Rating: 2
How much smaller can the chips become? Is there a threshold in that making it smaller would not be worth the while? Will we see 10nm in the future?

By livinloud on 5/25/2006 2:21:36 PM , Rating: 2
I Don't really know what is the smallest process we can go physicaly but I know that Intel and IBM and I assume AMD too are working on 45nm process since 2 or 3 years. It's in developpement and it's going to be reveal in 1 to 2 year depend on how goes the developpement. 10nm, we could see them but when no one really knows, could we reach maximum before that?

RE: How small can these chips get?
By smilingcrow on 5/25/2006 3:33:36 PM , Rating: 2
I think the shit hits the fan way before 10nm with current technology.

RE: How small can these chips get?
By kitchme on 5/25/2006 7:09:45 PM , Rating: 2
There are multiple problems once you get to that size. Nano world can help us out of it and having one atom control (open/close) gates. Now, that's small. Prob'ly not before 10-15 years.

65nm, eh?
By Howard on 5/26/2006 2:06:53 PM , Rating: 2
I hope the new CPUs will be able to hit over 3GHz.

Could I get some Thunderbird v Brisbane benches plez?
By Fnoob on 5/31/2006 10:32:11 PM , Rating: 2
Dude, my dual-1600Mp's (once unlocked) hit 3ghz back 5 years ago with (stupid insane) cooling.

Until they burnt (coolant leak). Years later though...

By Garreye on 6/1/2006 6:03:07 PM , Rating: 2
I think he was referring to stock AMD processors....and considering that there at 2.8 on 90nm, I'm fairly confident they will reach over 3 GHz

By Fnoob on 6/2/2006 8:29:57 PM , Rating: 2
I'm sure you are right on both counts.

The question is, after 3Ghz what's next? Will they continue to expect us to lap up "ever decresasing increases" so to speak. After all, a doubling of performance (6 GHz) seems a bit distant. Murphy and Moore were both bastards. I dont think we'll be seeing 6 - 12 - 24 GHZ any time soon. 24 processors, now thats a different story...

duhh! the name here give me the headache...
By nangryo on 5/24/2006 7:40:30 AM , Rating: 3
San Diego, Toledo, Venus, Denmark, Venice, Sparta, Santa Rosa, Santa Ana, Tyler, Sherman, Taylor and Keene

OMG... so much of them that lingering in my head. Could someone give a link that show the simplified diagram of this roadmad?

Really .. it's hard for people who do not keep up with this thing...

RE: duhh! the name here give me the headache...
By Xavian on 5/24/2006 8:11:42 AM , Rating: 2
San Diego and Venice are the current Athlon 64 single core processors that are out atm (same chips but San Diego is the 1MB cache version, Venice is the 512KB cache version)

Toledo and Manchester are the current Athlon X2 processers (Toleda the 2MB cache version and the other 1MB cache)

Denmark is the Dual Core opteron (2MB cache version)

as for the rest i can only assume they are either AM2 versions or future athlon chip codenames

By Zoomer on 5/28/2006 11:13:01 PM , Rating: 2
Venus is basically the opteron version of san diego.

By dgingeri on 5/24/2006 11:11:24 AM , Rating: 2

intel core is almost ready, AMD needs a new architecture.

They're working on it.....

By Griswold on 5/25/2006 4:22:27 AM , Rating: 3
Geez another one who didnt carefully read. K8L will have architectural changes. Nobody said its a new architecture.

There will be far more changes than what you listed.

Maybe go educate yourself by googling for it. I also advise you to read a nice article about conroe at AT where there are some clues as to what it takes AMD in terms of modifications to catch up without a new architecture.

I'm sorry...
By GoatMonkey on 5/24/06, Rating: 0
RE: I'm sorry...
By Spoelie on 5/24/2006 9:09:08 AM , Rating: 2
How about the memory controller, crossbar controller en ht links?

bah, all these names make me...
By Visual on 5/25/2006 11:41:10 AM , Rating: 2
... wanna just wait for the Zanzibar core.

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