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Polished next-gen. iteration of nanowire-based memory could offer speed, power, and density improvements

Stop us if you've heard this before: International Business Machines, Inc. (IBM) claims it's cooked up the super-memory of the future, which be smaller, better, faster, stronger than current designs.  

I. Starting the Race

The company demoed has at last demoed a full-fledged prototype of the device, dubbed "racetrack" memory.  "Racetrack" memory consists of one or more nanowire loops, each of which is partially magnetized.  

Within each wire, magnetized stripes represent the default on state -- a binary "1" or a "0" -- while demagnetized magnetic stripes represent the default off state.  When a current is applied, the magnetized regions "flow" down the wire (or "race", hence racetrack).  This allows the memory to be rewritten by a static head.  As there are no moving components, there'd likely be a reduced risk of failure, and possibly faster reads/writes contingent on the limiting material property -- the speed of the magnetic pattern flow along the nanowire.

Racetrack memoryRacetrack memoryRacetrack Memory
[Images Source: IBM]

IBM research fellow Stuart Parkin devised the concept back in 2002 and by 2004 had received a patent on some of the underlying principles.  An early prototype was implemented around 2008, but that prototype had the magnetic writing heads and wire current controls tied to external circuitry, while the nanowires were housed in a piece of test silicon.  The lab-bench style prototype was far from a realistic implementation.

II. Back on the Racetrack, Now Inside an IC

Now IBM has manufactured a CMOS circuit composed of 10 micrometers long, 150 nanometers wide, and 20 nanometers thick nanowires.  The thinnest diameter of a human hair is ~8.5 micrometers [source], so at least 180,000 of the nanowires could fit within the cross section of a human hair.  Also present in the new fully integrated design are the appropriate controllers and polarizable heads, which allow for writing to the "tracks".

Racetrack Chip
IBM has finally achieved an integrated circuit form factor for its racetrack memory.
[Image Source: IBM]

CMOS (complementary metal-oxide semiconductor) is a widely used circuit production technique, so the new second-generation prototype could be manufactured cheaply at standard chip fabrication facilities.  The crucial step would be depositing the nickel-metal alloy and then etching with acid to leave behind nanowires.

Professor Parkin describes the integrated prototype commenting, "All the circuits were separate from the chip with the nanowires on.  Now we've been able to make the first integrated version with everything on one piece of silicon."

III. Poor Materials Make This a "One Car" Race

The only outstanding issue for the prototype is that it was only tested writing one bit stripe per nanowire.  IBM blames this "one car race" on the poor performance of its soft magnetic material, nickel-iron.  

Magnetic meteorites
The magentic nickel-iron mix found in the current gen racetrack memory is a nanoscopic peer to magnetic nickel-iron meteorites.  But it's unfortunately not a very good reliable material for the job. [Image Source: First Point Minerals]

Professor Parkins is leading a team of researchers at IBM's Almaden, California research facility, investigating alternative materials.  They're currently testing a hard magnetic material, which derives its magnetism from its crystal structure.  They claim the initial performance they're seeing is much better.

IBM Almaden
The lobby of IBM's Almaden, Calif. research center, the birthplace of racetrack memory. [Image Source: Sydney Morning Herald]

Comments Professor Parkins, "Using this different material, we have discovered we can move the domain walls [between magnetic stripes] very fast and that they are much smaller and stronger than in the soft magnetic material used in the integrated devices.  I call this racetrack 2.0."

But there's some friendly competition in this race.  The Institute of Fundamental Electronics in Orsay, France -- a collaboration between the University of Paris SUD and the Le Centre national de la recherche scientifique (CNRF), the French national research center (think U.S. national lab) -- have a team actively working on testing new racetrack designs with novel materials.

Racetrack memory
A peek at the standard interface to the IFE's racetrack memory chip: the French research institution is work on trying to find a better magnetic material for the device.
[Image Source: IFE]

Dafiné Ravelosona, a Ph.D researcher at the institute, praised the work by IBM, but also pointed to the single bit flaw, opining, "It's a nice demonstration that shows it's possible to make this kind of memory using CMOS.  They have only demonstrated that it is possible to move a single bit in each nanowire."

His team hopes to find the perfect nanowire material before IBM does.

The important fundamental questions to ask regarding whatever material the two groups concoct are:
1.  How good are the material properties?
2.  How abundant is the material? (i.e. How cheap is the material?)
3.  How easy is the material to adapt to common silicon fabrication processes?

IV. Spintronics v. the HP Memristor

While "spintronics" (spin as in "magnetic spin" + "electronics) solutions like racetrack memory represent one potential answer to the future memory riddle, other parties have competing ideas.

IBM's enterprise hardware rival Hewlett-Packard Comp. (HPQ) is racing to bring its own novel solution -- memristors -- to market.  First realized by HP in 2008, the memristor also relies on nanowires.  But rather than nickel-iron, titanium dioxide (TiO2) is used.  

And rather than storing data as strips of magnetized atoms on a long nanowire, the memristor stores data as a resistance value.  The resistance is controlled by current, which causes a directional drift in Oxygen electron vacancies.  After enough current, enough of the vacancies shift to reach a steady state resistance in a certain direction.  The device can be "read" by checking the voltage at low current (V=iR), while the data (the resistance value) can be set by applying a current to either increase the resistance towards the maximum or a reverse current to decrease it.

Memristor under the microscope
A memristor chip under the microscope at HP [Image Source: HP Labs]

HP's technology has some advantages to spintronic solutions.

The memristor is closer to market, with HP predicting a H1 2013 hardware launch.  Flexible memristors (using titanium dioxide gel) have also been demonstrated, meaning the technology could be applied to coming flexible electronics applications, like bendable smartphones.  By contrast racetrack memory is much farther from the market, with no finite timeline for a market launch as the hunt for ideal magnetic material continues.

HP's claims might raise skepticism, but the company has published data supporting that its second generation design has achieved ~1 GHz switching times for a 3 nm x 3 nm memristor, with hole thermal velocity of 1 m/s.  This defies critics who claimed the material would switch too slow to be a feasible memory replacement (claims that were supported by silicon nanowires' higher hole thermal mobility of up to 165,000 m/s at room temperature).

The memory product is expected to be dubbed resistive random access memory (RRAM) when it hits the market.

V. Memristors Double as Computers

The memristor also can also be used with common metal wires to create a replacement to the transistor.  By adding crossing metal nanowires:

A memristor
A memristor in "crossbar latch" configuration [Image Source: HP]

With memristors in between acting as reprogrammable interconnects, the resulting "crossbar latch" circuit can act as any of the traditional logic gates, and together can be chained together to produce larger fundamental circuit elements, like the half adder.
half adder
The memristor half-adder [Image Source: Wikipedia]

Additionally, there are already two approaches to producing circuits with crossbar latches -- one of which uses more bars to produce a purely digital design, and a second of which uses fewer bars for an analog design, that "adds" the incoming signals passing them through a summing amplifier before undergoing analog to digital conversion.  The dueling approaches could drive performance of each to new heights.

Think of memristor crosslatch circuits as a field-programmable gate array (FPGA) on steroids -- a device literally reprogrammable at the transistor-analogue level.  That capability makes the memristor potentially more ubiquitous and hence cheaper than alternatives like racetrack memory.

Memristor Neurochip
Boston University has worked with HP to develop a memristor powered, reprogrammable chip which mirrors a neuron. [Image Source: Boston University]

VI. Other Players Still in the Race

And there's a host of alternative storage technologies also via for the spotlight:
  • Millipede Memory
    Basics: Also by IBM, stores data as nanoscopic pits Advantages: High, fully scalable density
    Disadvantages: Density is being outpaced by advances in traditional hard drives, moving components risks reliability.
  • NRAM ("Nano Ram")
    Basics: Carbon nanotubes "touch" when activated, separate when nonactive
    Advantages: Low power, permanent currentless storage, DRAM-like density
    Disadvantages: Nanotubes are expensive
  • SONOS/SHINOS
    Basics: A mix of silicon, oxygen, and nitrogen, charge is stored in Si3N4 crystal.
    Advantages: Low gate voltage, faster write speeds, fewer defects (longer life)
    Disadvantages: underdeveloped, leading to deficient areal density.
  • PMC
    Basics "Programmable Metalization Cell" (aka. Nanobridge/electrolytic memory/conductive-bridging RAM)
    Advantages: possibility of super-small scale, low power, and low materials cost
    Disadvantages: Production process is problematic with current fabs.
  • FeRAM**
    Basics: "Ferroelectric RAM" is similar to DRAM, but uses a ferroelectric material in its capacitor's dielectric
    Advantages: 1 ns (fast) switching, uses existing DRAM fab facilities
    Disadvantages: Shrinking gate to modern <50 nm scales without disrupting ferroelectric properties been a problem, preventing widespread commercialization, despite an early 1980s market entry.
  • MRAM/SPRAM**
    Basics: Resistance based cell designing using two magnetic plates, one permanent, one reprogrammable. (also known as: "Spin-Torque Transfer RAM")
    Advantages: Does not degrade, is faster than DRAM, and uses little power.
    Disadvantages: Adjacent cells disturb each other, limiting scaling.
  • PRAM*
    Basics: "Phase change memory", uses special chalcogenide glass material which when exposed to current heats and becomes amorphous.
    Advantages: Degrades slower than flash, fast-switching, and scalable
    Disadvantages: Thermal-sensitive, even higher programming current than flash, can't be preprogrammed.

*     = FeRAM:
First Sold in 1988 by  Fudan Microelectronics Co., Ltd. (HKG:8102) (the FM1208)
**   = MRAM: First sold in 2005 by Freescale (today sold under Everspin spinoff)
*** = PRAM: First sold in 2006 by BAE Systems Plc. (LON:BA)

A comparison of commercialized future flash designs [Kanhoe Xue/University of Colorado]

All of these technologies are competing with the rapidly advancing silicon-based flash memory and with the slow but widespread/cheap magnetic hard disks.  Until flash and/or magnetic hard drives hit their "storage wall" (a cessation of improvements to areal density, power, and reliability), these technologies will have to attempt to pass a moving target, a tough task.

For a more technically in-depth review of future memory technologies and how they stack up versus good old flash, I recommend University of Colorado Ph.D graduate Kanhoe Xue's excellent doctoral thesis [PDF], which summarizes the state of the art.  Professor Xue is now working at a research lab in France.

Source: TechnologyReview



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RE: Socket 7 Pentium?
By JasonMick (blog) on 12/7/2011 4:41:18 PM , Rating: 2
Good points, both of you, I didn't initially recognize it, but now that you mention that, it does look familiar. I've amended the text to clarify that it was the interface package (likely) not the chip itself. The image was posted on the group's website, so I mistakenly believed it to be the chip. Thankfully I have some very informed readers!


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