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Rajeeb Hazra, General Manager of Intel's Technical Computing Group holding “Knights Corner”
Over 1 TeraFLOPS on a single chip

GPGPU and cloud computing have been hot topics for the last several years. Intel has shown off several designs like Larrabee and the Single-chip Cloud Computer in the past. However, it is Knights Corner that will be the firm's first commercial product to use the Many Integrated Core (MIC) architecture. The co-processor will be offered as a PCIe add-in board.

The MIC concept is simple: Use architecture specifically designed to process highly parallel workloads, but ensure compatibility with existing x86 programming models and tools.

This would give MIC co-processors the ability to run existing applications without the need to port the code to a new programming environment, theoretically allowing maximum CPU and co-processor performance simultaneously with existing x86 based applications. This would dramatically save time, cost and resources that would otherwise be needed to rewrite them to alternative proprietary languages.

AMD and NVIDIA have been trying to do with their latest architectures by enabling support for languages like C++, but Intel wants to challenge them in this potentially lucrative market.

Knights Corner will be manufactured using Intel’s latest 3-D Tri-Gate P1270 22nm transistor process and will feature more than 50 cores. Intel demonstrated first silicon of Knights Corner at the SC11 conference yesterday. The co-processor wowed the crowd by delivering more than 1 TeraFLOPS of double precision floating point performance.

The firm also touted its "commitment to delivering the most efficient and programming-friendly platform for highly parallel applications", and showed off the benefits of the MIC architecture in weather modeling, tomography, protein folding, and advanced materials simulation at its booth.

There is no timeframe on when Knights Corner will enter production or be available to customers.




"And boy have we patented it!" -- Steve Jobs, Macworld 2007



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