IDF 2011: Intel Looks to Take a Bite Out of ARM, AMD With 3D FinFET Tech
September 13, 2011 10:15 PM
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New technology drastically reduces power, greatly improves performance
We're live this week at the
2011 Intel Developer Forum
, which is being held at the Moscone Center in San Francisco, Calif.
I. Go 3D or Go Home
, a senior research fellow at the world's biggest personal computer and server CPU maker, Intel Corp. (
), reviewed the
upcoming Tri-Gate transistor technology
. This technology is known by a few other names -- 3D metal–oxide–semiconductor field-effect transistor (3D MOSFET) and Fin Field Effect Transistor (FinFET), a term coined by
University of California, Berkley
researchers in a 1999
on 3D transistors.
Now 3D transistors aren't terribly new in terms of a research and development concept, with over a decade of work behind the devices. The important thing here is that Intel is the first company to be bringing this technology to the market, and if its claims hold true this technology may essentially negate any
that its competitors such as ARM chipmakers NVIDIA Corp. (
) and Qualcomm, Inc. (
) and x86 rival Advanced Micro Devices, Inc. (
) may hold.
If there's one silver lining for Intel's competitors, it's that Mr. Bohr essentially admitted that yields weren't currently at production levels, though he insists that his company "is always surprised by how much yields improve at the last second."
In other words the first 3D transistor product from Intel (the 22 nm
core) hasn't quite shipped yet. But if Intel can deliver, it's competitors may have cause for concern as the veteran chipmaker claims.
II. The Presentation
Ah, there's our speaker, Mr. Bohr.
So Mr. Bohr starts by refreshing our memory on how traditional MOSFET (transistor) scaling works. Basically, the rules of transistor scaling were pioneered by International Business Machines, Inc.'s (
) research fellow
Robert H. Dennard
in the 1970s. The idea is that all transistors share basically the same design, with key structural features such as a gate, a source, and a drain. With each die shrink, all of these features scale by some given fraction -- say 0.7 (the example Mr. Bohr used)
This scaling worked pretty well up until recently. Die shrinks slowly improved transistor performance and brought down costs to the level where consumers can today obtain a PC CPU with what was once supercomputer processing power for under $100.
However, at very small sizes (e.g. 90 nm or less) transistors begin to waste more and more power with each die shrink. This is due to two kinds of leakage current, gate oxide leakage and subthreshold leakage. The gate oxide leakage is present when the transistor is switched on; the subthreshold leakage is present when it's switched off.
It's here that the problems for Intel and it's rivals begin.
Intel's first solution to the problem of leakage was to create strained silicon transistors on the 90 nm node back in 2003.
In 2007 Intel introduced
, a line of 45 nm CPUs that brought another nifty trick -- hafnium based high-K dielectrics.
Between strained silicon and the high-K dielectrics (which Mr. Bohr would later say the competition is still "struggling to get right") Intel was able to sustain performance gains for a bit longer. But it would need a new trick to keep things going at the 22 nm node, where leakage was an even bigger issue than ever before.
So Intel turned to the Tri-Gate transistor. As early as 2002, Intel's R&D labs had been working on this type of complex device.
Mr. Bohr recalls that at IDF 2009, Intel CEO Paul Otellini showed off working 22 nm SRAM. He says that Mr. Otellini "didn't mention tri-gate in 2009" as Intel "didn't want to show its hand" to competitors.
Now Intel believes it can begin production on the complicated design by the end of the year -- Q4 2011.
So what is a 3D transistor? To understand here's what a normal transistor looks like. Note the source and drain are separated by a thin layer under the gate. Current flows along the surface of this layer based on the input to the gate.
In the FinFET, the source and drain are raised fin-like structures. Current now travels along all three protruding faces of the surface-to-drain moiety.
Multiple transistors can share a common gate and common contacts, for easy construction of dense logic circuits.
Intel shows off pictures of the 22 nm 3D transistors and how they appear starkly different from a visual perspective from their predecessor, the 32 nm planar transistor.
Mr. Bohr was unequivocal about Intel's decision to fully throw out the planar transistor in new chip designs. He states, "We have only tri-gate transistors, we have no planar transistors."
One way the tri-gate transistor reduces leakage is by using a fully-depleted fin. This differs from the standard planar transistor, in which there's typically a voltage between the substrate and the gate oxide, resulting in leakage current flow and power waste.
Tri-Gate transistors can reduce the channel current to next to nothing. But the better approach from a power savings perspective is to use the gains to stick with current channel current levels, but reduce the required gate voltage.
Intel's 22 nm FinFET are 37 percent faster (in terms of gate delay vs. 32 nm planar chips) when the operating voltage is held constant. In other words, in performance CPUs, you'll be able to use the same amount of power and see much faster performance. Intel was careful to note that this effect is more accentuated at the low voltage end (the 37 percent is for an operating voltage of 0.7 V) versus the high voltage end (Intel said at 1.0 V, the increase would be more like 18 percent).
The flip side of the coin is that you can keep the same time, but cut the power used by approximately 0.2V. When that adds up over billions of transistors, each using small rations of current, that can yield big power savings.
(Note: Intel included the gray line to show what 22 nm planar transistor performance would have looked like -- good, but not as good as the FinFETs.)
The chipmaker will now be offering its design team three separate kinds of transistors -- higher leakage (~100 nA/um), high power (HP) transistors, capable of the fastest frequency; moderately fast transistors -- standard power (SP) -- with relatively low leakage (~1 nA/um) and the very lowest power (LP) transistors (~0.02 nA/um), which will only be capable of supporting lower clock frequencies.
Intel sees the HP transistors predominately used in servers and desktops, the SP chips in ultrabooks/tablets, and the LP chips used in pocket devices (e.g. smartphones).
The company breaks down this strategy yet again...
Intel says it will offer chipmakers a "buffet" of options in terms of performance versus power consumption versus price. Presumably it's talking primarily about its internal chip design teams, but an exchange with Mr. Bohr led us to believe that very large partners may be able to sway Intel into producing specialized designs.
Some may find Intel's internal codenames for the 32 nm, 22 nm, and 14 nm nodes interesting. What's more interesting is that Intel plans to produce two different varieties of chip at each node -- a stand alone CPU (think traditional CPU) and a system-on-a-chip (complete with integrated graphics, RAM, etc.).
Intel emphasized that there were other differences between the CPU and SoC. For example the SoC uses high voltage I/O transistors, while the CPU does not. This higher voltage presumably allows for a lower peak current.
As we mentioned, the tri-gate transistors will launch with
in H1 2012.
Intel plans to carry out the manufacturing of the chips at five fabs. Currently, only the D1D Oregon fab -- an R&D-heavy facility -- is capable of producing the complicated designs. Intel clearly has its work cut out for it.
States Mr. Bohr, "There were very clear challenges [to production] a year ago."
He says yields are still not at production-ready levels.
Intel blasted competitors in this slide. It says it beat them to strained silicon, it beat them to high-K dielectrics, and it's now beaten them to FinFETs. Intel says it's confident that its rivals won't release FinFET designs until at least 2015, giving it three years of unrivaled market time.
Intel singled out rivals
Electronics Comp., Ltd. (
Taiwan Semiconductor Manufacturing Company (
), and GlobalFoundries Inc. as being laggards.
Note GlobalFoundries makes AMD's CPU chips, while the other named parties make the majority of the ARM chips found in tablets and smartphones.
Intel says its competitors are falling farther behind with each new technology, using their planned deployment targets for strained silicon, high-K dielectrics, and FinFETs as evidence.
Mr. Bohr concluded stating, "Our competitors are still on a planar design at their 22 nm process, which will just not be able to keep up in power and performance."
Mr. Bohr may be right. If Intel can get yields up, and if it's being forthcoming about how dramatic the power efficiency gains (via leakage reduction) are
looks poised to dominate the personal computer market.
And once Intel can bring this technology to the Atom lineup -- which it hopes to do in 2013 -- it will have essentially nullified the ARM architecture's greatest advantage.
Of course even if Intel can deliver superior chips to ARM in the mobile space, it may still be at a disadvantage from a business perspective, given how entrenched ARM is. For example, 25 percent of smartphones currently sold and approximately 60 percent of the tablets currently sold are Apple, Inc. (AAPL) devices. Apple has shown no desire to switch from ARM to x86.
Thus Intel may find itself in a similar situation to AMD at the debut of the Opteron chip -- it may have the better product, but face trouble gaining ground in an entrenched market.
The real pity here is that Intel thus far refuses to consider -- at least publicly -- producing an ARM CPU. When it comes to mobile devices, which tend to be able to get by on a smaller instruction set, etc. there's certain inherent power efficiencies granted by adopting an ARM architecture. In short Intel is competing based on its process, while ARM is competing based on its architecture.
One can only hope that Intel might have a change of heart and find a way to license ARM core designs (either via an acquisition or a new licensing petition) and merge the Tri-Core technology with ARM ahead of its rivals. Now that would truly be the best of both worlds.
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it's not 0.7 percent for die shrink...
9/14/2011 11:07:18 AM
"With each die shrink, all of these features scale by some given percentage -- say 0.7 percent (the example Mr. Bohr used)"
I think you misheard what he said. Each generation shrinks features by 0.7x of the previous generation...not by 0.7%. That's why they call them 65nm, 45nm, 32nm, etc. nodes.
RE: it's not 0.7 percent for die shrink...
9/14/2011 11:23:01 AM
Just to expand on what you said, the 0.7x isn't arbitrary, it's half the area of the previous node.
For instance, if you want half the area per transistor, you'd shrink the x and y dimensions by sqrt(2), or 1.414.
90nm/sqrt(2) = 64nm
65nm/sqrt(2) = 46nm
45nm/sqrt(2) = 32nm
So on each new full node you can pack twice the transistors per area as the previous node.
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