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32nm Planar transistor on the left versus 22nm 3D Tri-Gate transistor on the right. The yellow dots represent current flow.  (Source: Intel)

The 22nm 3D tri-gate transistor   (Source: Intel)
New 22nm 3D Tri-Gate transistors will boost performance by up to 37 percent compared to existing 32nm technology

When it comes to making advances in manufacturing technologies for semiconductors, we can always look to Intel to lead the way. Today is no exception as the Santa Clara, California-based company announced today that it will incorporate 3D transistors into its upcoming 22nm microprocessors. 

Intel says that its 3D transistor design, which it calls Tri-Gate, marks the first time that a three-dimensional structure has been incorporated into high-volume production. Ivy Bridge will be the first recipient of Tri-Gate.

"Intel's scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension," said Intel President and CEO Paul Otellini. "Amazing, world-shaping devices will be created from this capability as we advance Moore's Law into new realms."

Intel goes on to describe 3D Tri-Gate as follows:

The traditional "flat" two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top -- rather than just one on top, as is the case with the 2-D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the "on" state (for performance), and as close to zero as possible when it is in the "off" state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance). 

Just as skyscrapers let urban planners optimize available space by building upward, Intel's 3-D Tri-Gate transistor structure provides a way to manage density. Since these fins are vertical in nature, transistors can be packed closer together, a critical component to the technological and economic benefits of Moore's Law. For future generations, designers also have the ability to continue growing the height of the fins to get even more performance and energy-efficiency gains.

Tri-Gate will provide unprecedented levels of performance and power savings according to Intel. The technology will allow processors to run at lower voltages while at the same time limiting the amount of leakage current. In fact, Intel says that processors using 22nm Tri-Gate transistors offers up to a whopping 37 percent performance boost at low voltages.

Naturally, higher performance at lower operating voltage will do wonders in Intel's never-ending quest to chase down low-power ARM chips with its Atom-based processors.

"The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next," said Intel Senior Fellow Mark Bohr. "It will give product designers the flexibility to make current devices smarter and wholly new ones possible. We believe this breakthrough will extend Intel's lead even further over the rest of the semiconductor industry." 

Ivy Bridge processors using Intel's 3D Tri-Gate technology will enter production later this year. You can watch a YouTube clip on 3D Tri-Gate here.



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RE: Confusing
By EricMartello on 5/4/2011 5:23:53 PM , Rating: 2
They're called 3D because rather than simply shrinking a typical transistor even further (to the point where quantum weirdness occurs), the transistors improve performance by "stacking" additional gates within the same "footprint". In other words, the CPU is getting a few nanometers taller, but you could theoretically double or triple the number of transistors per core without having to shrink them down.

A questionable analogy for this would be to think of 3D transistors to regular transistors as Multi-core CPUs to regular CPUs, in the sense that both a multi-core CPU and regular CPU fit into an identically sized socket, yet the multi-core CPU offers greater performance with its additional cores.


RE: Confusing
By LRonaldHubbs on 5/4/2011 5:47:20 PM , Rating: 3
Well, sort of. They are improving performance by wrapping the gate around three sides of the channel instead of just one. As you can see in the picture above, this actually comes at an area penalty since what could have been a single diffusion bed now has to be split up into narrower pieces. Where a multi-fingered FET in currently technology would look like a solid rectangle with gates across the surface, it now looks like a waffle and must be bigger to achieve the same net channel width. However , since the channel is gated from three sides, they can now add a height component as well as width, which apparently regains more than the lost area.

Rather than calling this stacking, I would liken it to the perpendicular bit revolution that happened in hard disk platters several years back.


RE: Confusing
By AnnihilatorX on 5/5/2011 5:48:55 AM , Rating: 2
I agree. This should be called perpendicular encompassing gate or something like that.

If they use the word 3D now, a true 3D stacked transistors chip will be called what? 4D?


RE: Confusing
By EricMartello on 5/6/2011 7:14:36 PM , Rating: 2
quote:
Well, sort of. They are improving performance by wrapping the gate around three sides of the channel instead of just one. As you can see in the picture above, this actually comes at an area penalty since what could have been a single diffusion bed now has to be split up into narrower pieces. Where a multi-fingered FET in currently technology would look like a solid rectangle with gates across the surface, it now looks like a waffle and must be bigger to achieve the same net channel width. However , since the channel is gated from three sides, they can now add a height component as well as width, which apparently regains more than the lost area.

Rather than calling this stacking, I would liken it to the perpendicular bit revolution that happened in hard disk platters several years back.


In a nutshell they're being stacked to cram more transistors into the same amount of space without having to shrink them down any further - which is what I said. Let's keep the explanations simple lest ye wish to start an AMD vs Intel battle.


RE: Confusing
By LRonaldHubbs on 5/18/2011 8:01:30 AM , Rating: 2
No, they aren't. I was polite in my initial response, but what you said is wrong. Nothing is being stacked here in the z dimension, the circuits still reside in the x,y plane. All they are doing is turning the gate on it's side so that it is now vertically oriented, which lets them fit more FETs side by side in the same 2D space.

There is a different 3D technology, which you seem to be confusing, in which multiple circuit layers get stacked on top of each other. It's called 3DIC, and it is not what this article is about.


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