Reprogrammable Coprocessors For Any Opteron Server
April 24, 2006 2:40 AM
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The DRC module plugs directly into a Socket 940 AMD Opteron motherboard
DRC has announced its newest FPGA that drops into AMD's Socket 940
The Register has a fairly
in depth look
at one start-up's attempt to capitalize on AMD's HyperTransport interface -- a reprogrammable coprocessor that can drop into any Socket 940 socket. The company, DRC, built its programmable coprocessor on Xilinx Virtex4 field programmable gate array integrated circuits.
For specialized industries, a dynamic coprocessor is exactly what the doctor ordered; low overhead for extremely specific tasks such as vector math or collision detection. Companies already pay thousands to millions of dollars to have such overly specific algorithms ported to custom FPGA processors, but the kicker for DRC is that the chip can be integrated into a multi-slot Opteron server running the correct software.
Each series of coprocessors
unveiled by the company
uses the standard HyperTransport (HT) interface to communicate with the main processor. The low end coprocessor, the DRC100-L60ES, uses a 200MHz by 8-bit HT link. DRC's two high end modules, the DRC100-L60 and the DRC110-L160 both use a 400MHz by 16-bit interface instead. DRC coprocessors range in size from 50,000 to 140,000 programmable gates and all three can utilize 6.4GBps between the Xilinx FPGA and the DDR400 memory bank.
Each DRC module starts at about $4,500. Competing proprietary systems from SGI and IBM easily cost four times that and generally require additional proprietary hardware and contracts to support.
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RE: Calc types
4/25/2006 8:56:49 PM
"As I'm sure you are aware, FPGAs are ONLY "much slower" in CLOCK SPEED (compared to Pentium, Opteron etc)."
In what other way can a transistor be slower?
"However, they have the benefit of MASSIVE PARALLELISM (millions of gates), and amazing internal memory bandwidth,"
You're not making sense. FPGAs have far fewer transistors then conventional fabbed chips. Given the same verilog code, the FPGA will always be an order of magnitude slower then what a fab would give you.
The advtange is reprogrammablity and lower setup costs. You can fix your mistakes, and be up and running again in hours, not months if you find a bug. For that you lose speed.
" plus customisable operations that are not in the instruction set of x86 processors."
What the heck are you talking about? FPGAs are a way you can implement processors, including x86 ones, not a rivial to x86.
" Therefore in many technical applications, FPGAs can deliver excellent acceleration, despite the seemingly low clocks."
Ok, but that has nothing to do with whatever you're talking about. The clock speed is just the cost you pay for flexibility.
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