Reprogrammable Coprocessors For Any Opteron Server
April 24, 2006 2:40 AM
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The DRC module plugs directly into a Socket 940 AMD Opteron motherboard
DRC has announced its newest FPGA that drops into AMD's Socket 940
The Register has a fairly
in depth look
at one start-up's attempt to capitalize on AMD's HyperTransport interface -- a reprogrammable coprocessor that can drop into any Socket 940 socket. The company, DRC, built its programmable coprocessor on Xilinx Virtex4 field programmable gate array integrated circuits.
For specialized industries, a dynamic coprocessor is exactly what the doctor ordered; low overhead for extremely specific tasks such as vector math or collision detection. Companies already pay thousands to millions of dollars to have such overly specific algorithms ported to custom FPGA processors, but the kicker for DRC is that the chip can be integrated into a multi-slot Opteron server running the correct software.
Each series of coprocessors
unveiled by the company
uses the standard HyperTransport (HT) interface to communicate with the main processor. The low end coprocessor, the DRC100-L60ES, uses a 200MHz by 8-bit HT link. DRC's two high end modules, the DRC100-L60 and the DRC110-L160 both use a 400MHz by 16-bit interface instead. DRC coprocessors range in size from 50,000 to 140,000 programmable gates and all three can utilize 6.4GBps between the Xilinx FPGA and the DDR400 memory bank.
Each DRC module starts at about $4,500. Competing proprietary systems from SGI and IBM easily cost four times that and generally require additional proprietary hardware and contracts to support.
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RE: my first thought...
4/24/2006 5:05:42 PM
In all probability a Xilinx FPGA (indeed several of them) or the equivalent Altera solution, was what they will have used to PROTOTYPE the design of the Physx chip. Once you have the design right, unit costs are much cheaper (apart from a one-time NRE nonreturnable engineering cost) by blowing the design in to a custom ASIC (application specific integrated circuit) and indeed that is what they have done. The ASIC based design will run a little faster too. However, ASICs cannot be reconfigured in the way that FPGAs can so they have less flexibility to correct errors or improve the design and lack the ability to optimise particularly for the current job in hand.
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