Print 65 comment(s) - last by saratoga.. on Apr 28 at 12:51 AM

June 6, 2006 didn't fit AMD's schedule

We just got official confirmation from motherboard and chipset manufacturers in Taiwan -- AMD has moved the official launch date of Athlon 64 DDR2 up two weeks to May 23, 2006. AMD roadmaps have previously put the AM2 launch at June 6, 2006 (during Computex 2006), but since motherboards and CPUs are already completed, the launch will be pushed up. AMD insiders tell us Conroe's launch date was also a factor in pushing the AM2 launch date up, though even we do not know the exact date Intel's Conroe will launch.

AMD's latest advisories claimed the following:
  • May 16, 2006: Global announcement of Energy Efficient Processor roadmap and pricing
  • May 23, 2006: Global announcement of Socket AM2 and new desktop product availability and pricing
  • May 31, 2006: Global announcement of AMD LIVE! desktop system availability

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RE: .
By saratoga on 4/28/2006 12:50:11 AM , Rating: 2
I think it's less impossible than you think. But it would blur the line between wether or not it's two seperate cores or one core with 'hyperthreading'.

I think you overestimate your understanding of how complicated parallel processing really is.

There are already dual core CPUs that share cache.. you just need to set it up so they can share registers, and this could be doable.

I don't even know what to say. Sharing registers is the least of the concern here. HT can already do that just fine. Hell there have been machines doing that for years. The problem is, once you have two cores, how do you exact useful work from one thread on both cores? Essentially, the answer has been "you don't".

Or at best you do some hack like speculative execution or have one prime up the cache. Neither is all that appealing though if you're concerned about heat.

For the record, 'branches' in code are much more low-level than flowchart 'branches' in AI. AI would do better by running each 'AI' as a separate thread, and let the CPU's paralellism run as many as possible.

Well, the branches on a flow chart are often implemented as a single cpu branch, so I don't know about that. I'd say they can be more complicated, but typically, an if statement can be mapped directly to a branch (or at least a few compares and then a branch depending on the machine and how powerful it's instructions are).

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