AMD Bumps AM2 Launch Date
April 19, 2006 2:05 AM
comment(s) - last by
June 6, 2006 didn't fit AMD's schedule
We just got official confirmation from motherboard and chipset manufacturers in Taiwan -- AMD has moved the official launch date of
Athlon 64 DDR2
up two weeks to May 23, 2006. AMD roadmaps have
previously put the AM2 launch at June 6, 2006
(during Computex 2006), but since motherboards and CPUs are already completed, the launch will be pushed up. AMD insiders tell us Conroe's launch date was also a factor in pushing the AM2 launch date up, though even we do not know the exact date Intel's Conroe will launch.
AMD's latest advisories claimed the following:
May 16, 2006: Global announcement of Energy Efficient Processor roadmap and pricing
May 23, 2006: Global announcement of Socket AM2 and new desktop product availability and pricing
May 31, 2006: Global announcement of AMD LIVE! desktop system availability
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RE: reverse hyperthreading?
4/19/2006 4:35:39 PM
"but it is exactly this point which make R-HT (reverse-hyperthreading) not BS and in fact may be feasible. "
How can you say that? We don't even know what it is. That link says nothing at all about what it does or how it works.
" "IF" AMD can make the two 3-wide cores appear as a single 6-wide core then it may translate to improvements. although this analogy would make two 2.0 ghz 3-wide cores into one 2.0ghz 6-wide core and not a 4.0Ghz 3-wide core in the process. "
I doubt thats what Reverse HT would do, since that is complete horse shit and could not actually be built. At least not in the sense you're thinking. The best you could do would be to build a 6 issue core, and give it two way SMT, and then call it two 3 issue cores. Of course, thats not so much "reverse HT" as it is "actual SMT" :) And yes, I am a computer engineer.
My guess is the actual system is just some sort of speculative execution that runs ahead of the main thread to prime the cache. Sun looked into such a system a while back. Its doable, but wastes enough power that I doubt it'd be very attractive unless you had a very low power system that wasn't ramping in clock speed like you wanted (which might be the K8, but I kind of doubt it).
RE: reverse hyperthreading?
4/19/2006 5:18:44 PM
"How can you say that? We don't even know what it is. That link says nothing at all about what it does or how it works."
That's true, we don't know what it does. There are only speculations about it. What is said about it though is that it tries to use two cores to emulate one core. That being said, it may be indeed speculative execution but it is also possible that it may be making 2 cores appear as one wider core.
"I doubt thats what Reverse HT would do, since that is complete horse shit and could not actually be built. At least not in the sense you're thinking. The best you could do would be to build a 6 issue core, and give it two way SMT, and then call it two 3 issue cores. Of course, thats not so much "reverse HT" as it is "actual SMT" :) And yes, I am a computer engineer."
you are entitled to your own opinion whether it can be built or not. Oh and Mr computer engineer, if they built ONE six-issue core how can they give it SMT if it only had ONE core to begin with. ??? They can build two 3 issue cores and add SMT to the TWO cores but that is almost no different from current dual core CPUs.
RE: reverse hyperthreading?
4/19/2006 6:39:09 PM
SMT refers to presenting the functional units of a core as separate logical processors. This allocation of execution resources can be done concurrently to compensate for a lack of ILP in the code being scheduled or sequentially to hide stalls caused by dependencies. There is no contradiction in providing SMT to a single-core processor. That however wouldn't be "reverse hyperthreading," it would be SMT.
Making a parallel execution engine appear to the software being run as a sequential execution engine isn't in of itself novel. That is what superscalar cores do already. A lot of hardware is added to decode, re-order, and speculatively execute instructions in parallel and present state that appears to be modified sequentially. As everyone knows--and this is the motivation of SMT in the first place--in certain types of code there is little ILP that can be obtained and functional units are left underutilized. Working with a simulator and sample code an engineer can model the effects of issue-width on the number of cycles necessary for executing code. When performing this modeling the engineer will find that while the size of the circuitry grows quadratically with issue width, performance does not. For typical code, as the issue width tends toward infinity, the rate of improvement tens toward zero. Naively increasing the issue width thus won't solve any problems, because the code being executed doesn't contain sufficient ILP.
Taking two n-issue cores and naively adding the necessary scheduling and re-ordering hardware to make them appear as a single core will never provide the same performance of a 2n-issue core. You're reducing the space complexity of an actual 2n-issue device, at the cost of genuinely sharing the same resources. At the lowest-end you'll waste a lot of resources performing speculative execution that will be thrown away 97+% of the time. Somewhere in the middle you'll schedule work on both processors realizing that functional units on both are going to be underutilized because of limitations in scheduling and re-order possibilities caused by both cores sharing only some state. At the highest end you won't pretend to be a single processor but will instead present logical processors to the operating system where some of the functional units of one of the physical processors will be scheduled and the results re-ordered as if they belonged to the other physical processor. This way the functional units in the second processor are not wasted prematurely when there operating system has work for them to do. This is necessarily less optimal than SMT on a 2n-issue device, but the cost of producing the device is lower in design and manufacturing.
What AMD has in the future is a problem: their cores are probably going to trail Intel's by 15%, and they have only so many resources to devote to remaining competitive and designing future products. While enjoy a commanding performance and power dissipation lead for years, AMD has only enjoyed small increases in market share that could evaporate more rapidly than it was obtained if Intel suddenly starts just being better. They cannot financially afford that sort of problem.
What AMD has, is a multicore process that is working quite well for them. What they also have, is that a lot of the software people use isn't aggressively multithreaded. Even if they can't obtain 2x improvements in performance in these programs through scheduling and synchronizing work on two cores, perhaps they can obtain enough to remain competitive with Conroe on computationally-intensive tasks with a lot of ILP. If AMD's is doing anything but tossing feces on the wall in hopes of preventing post-IDF rumors from sabotaging their future, it's probably that.
"We basically took a look at this situation and said, this is bullshit." -- Newegg Chief Legal Officer Lee Cheng's take on patent troll Soverain
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