Samsung Announces 3D Chip Packaging Technology
April 13, 2006 9:34 AM
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Samsung Semiconductor becomes the first company to announced 3D memory packaging
Samsung just announced a new method to pack more memory into small spaces -- three-dimensional chip packaging. The technique works by adding "through silicon" interconnects on the memory module and then daisy chaining multiple modules through the interconnects. Samsung has dubbed this new technology "wafer-level stack process" or WSP.
Existing semiconductor packaging relies on wire bonding to a printed circuit board (PCB). The wire bonding requires space between the interconnects to eliminate interference, but ultimately becomes the limiting factor when attempting to create high density memory. "Through silicon" interconnects are essentially laser cut holes between the memory dice. The holes are later filled-in with a conductive material creating a vertical interconnect.
Samsung researchers managed to stack eight 2Gb NAND chips onto one package. The result is a 16Gb NAND chip that is just over half a milimeter in height. The same technology will also be used for DRAM later this year and multimedia controllers. Cell phone, PDA and high density server components are all the likely candidates for this new process. Samsung's newest NAND hard drive,
announced a few weeks ago
, would only be eight millimeters high if the WSP package allowed for all 256 modules to stack on the same packaging.
However, 3D packaging isn't the best route for chip assembly. On relatively slow NAND modules, the thermal envelope is not a huge factor. High speed DRAM, on the other hand, has much higher operating temperatures and will not likely adopt Samsung's WSP or other 3D packaging in the near future.
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4/14/2006 1:42:53 PM
"dice" is one possible plural for die.
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