Samsung Announces 3D Chip Packaging Technology
April 13, 2006 9:34 AM
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Samsung Semiconductor becomes the first company to announced 3D memory packaging
Samsung just announced a new method to pack more memory into small spaces -- three-dimensional chip packaging. The technique works by adding "through silicon" interconnects on the memory module and then daisy chaining multiple modules through the interconnects. Samsung has dubbed this new technology "wafer-level stack process" or WSP.
Existing semiconductor packaging relies on wire bonding to a printed circuit board (PCB). The wire bonding requires space between the interconnects to eliminate interference, but ultimately becomes the limiting factor when attempting to create high density memory. "Through silicon" interconnects are essentially laser cut holes between the memory dice. The holes are later filled-in with a conductive material creating a vertical interconnect.
Samsung researchers managed to stack eight 2Gb NAND chips onto one package. The result is a 16Gb NAND chip that is just over half a milimeter in height. The same technology will also be used for DRAM later this year and multimedia controllers. Cell phone, PDA and high density server components are all the likely candidates for this new process. Samsung's newest NAND hard drive,
announced a few weeks ago
, would only be eight millimeters high if the WSP package allowed for all 256 modules to stack on the same packaging.
However, 3D packaging isn't the best route for chip assembly. On relatively slow NAND modules, the thermal envelope is not a huge factor. High speed DRAM, on the other hand, has much higher operating temperatures and will not likely adopt Samsung's WSP or other 3D packaging in the near future.
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4/14/2006 2:17:42 AM
this doesnt really do anything for increasing the write cycle life expectancy so solid state hard drives might be another step away, but if this means that in a year I can get an 8GB thumbdrive for under $200 then you wont hear any complaints from me.
RE: Too bad..
4/14/2006 5:01:00 AM
I have a feeling that is already pretty close:
RE: Too bad..
4/15/2006 4:09:33 PM
What it does is allow manufacture to use cheap, low density dice (yes, dice) to build expensive, high density die. When the whole world is flooded with cheap slow, last generation flash, it will make the high end cheaper and consume the obsolete supply out there. Good move.
However, I would imagine it will be relatively expensive (all those work cost money) and it will only be used to build the super high end stuff from high end stuff, instead of build mid end stuff from low end stuff.
I think it is good for non-heat generating stuff like slow D-RAM (for server) and flash. It is not suitable for CPU.
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