Samsung just started producing DDR3 on its 40nm process last year, but is already working on its newest generational node. The company describes it as being 30nm-class, but is generally acknowledged as being around 32nm. The process size refers to the average half-pitch of a memory cell. A smaller die size means that more dies can fit on a silicon wafer, reducing production costs. The company estimates the new chips will increase its cost-efficiency per wafer by sixty percent.
 
The new 2Gb chip can be used to create power-efficient 4GB modules operating at 1.35 volts. Samsung expects power savings of 30 percent compared to a similar chip produced on a 50nm process, with a 4GB module consuming only three watts per hour when used in a newer-generation notebook.

“Our accelerated development of next generation 30nm-class DRAM should keep us in the most competitive position in the memory market,” said Soo-In Cho, President of Samsung Electronics' Memory Division.

Mass production of the new chips is expected to start in the second half of the year, with volume ramping up for the busy holiday shopping season.