IDF09: Intel Ready With Silicon From Next-Gen "Sandy Bridge" Architecture
September 22, 2009 2:43 PM
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Intel President Paul Otellini shows off a 300mm wafer containing Sandy Bridge chips
"Westmere" is only the first step, as "Sandy Bridge" will be where Intel really gets into 32nm.
The product launch of Intel's
may be just around the corner, but they aren't resting on their laurels.
, Intel's next-generation architecture, is already being produced in test batches at D1D in Hillsboro, Oregon.
D1D is Intel's development fab, and is used to decrease defect densities and increase yields before the line is duplicated in the firm's worldwide manufacturing network. Intel's President Paul Otellini showed off a 300mm
wafer during his opening keynote at the
Intel Developer Forum in San Francisco
Intel is currently focusing on ramping up production of
CPUs so that there will be sufficient quantities available when they go on sale in the fourth quarter of this year. Fab D1C and AFO (Aloha Factory Operations) will also ramp up
production in Q4.
Many people have questioned why Intel doesn't plan on releasing a quad-core
chip, instead going with a
six-core variant named
that will be paired with a 45nm graphics chip.
The answer is twofold. Intel will be capacity constrained on 32nm, with only a few fabs producing mainstream, high volume parts. Secondly, the main thrust of Intel's 32nm production will be in two major fabs which are currently undergoing expansion and retooling.
Intel's "Megafab", Fab 32 in Chandler, Arizona, will start 32nm production in late 2010, followed by Fab 11X in Rio Rancho, New Mexico. Fab 32 has a very large cleanroom at 320,000 square feet, but is eclipsed by Fab 11X's massive 370,000 sq. ft cleanroom.
will also feature a sixth generation graphics core on the same die as the processor core. It includes 256-bit AVX instructions for floating point, media, and processor intensive software.
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RE: round vs. square
9/23/2009 12:45:04 AM
Another reason for round wafer is mechanical stability. Round shape is stronger than rectangular shape. Such a big wafer can shatter very easily. Breaking a wafer with > 50 CPUs on it would cost a lot of $$$
"Intel is investing heavily (think gazillions of dollars and bazillions of engineering man hours) in resources to create an Intel host controllers spec in order to speed time to market of the USB 3.0 technology." -- Intel blogger Nick Knupffer
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