DailyTech has learned that JMicron will be unveiling a new NAND flash controller for use in Solid State Drives (SSDs) in the near future. The JMF612 chip uses an ARM9 core in a 289-ball TFBGA package, and will support the use of up to 256MB of DDR or DDR2 DRAM as an external cache.
The new chip was designed to remedy stuttering problems during random write operations, which has plagued SSDs using the JMF602 flash controller. JMicron rushed out a JMF602B chip to address shortcomings, but was only partially successful. Several firms decided to combine two JMF602B chips and an internal RAID chip from JMicron to boost performance. Although it raised costs significantly, it was still cheaper than controllers from Samsung and Indilinx, which were not yet available at the time. It was for this reason that SSDs like OCZ's Apex and G.Skill's Titan series were born.
The JMF612 chip is designed especially for a new generation of NAND flash chips built using smaller process geometries that will be entering the market soon. The new flash chips will be smaller, faster, and cheaper to manufacture. IM Flash Technologies, a joint venture between Intel and Micron, is already building 34nm NAND, while 32nm NAND from Samsung and Toshiba will soon be entering production. The use of a cheap single-chip controller and new higher density flash chips could cut prices in half by the vital Christmas shopping season.
SSDs using the chip will also be able to support Native Command Queuing (NCQ), which was designed to increase performance of SATA hard disks by allowing the drive to internally optimize the order in which read and write commands are executed. NCQ is used in SSDs when there is latency due to high CPU usage. It also supports 128-bit Advanced Encryption Standard (AES) protocols for full disk encryption. This provides data security mandated for classified and/or privileged information in government and corporations.
While most drives using the new chip will be designed for its SATA II interface in mind, it does have a USB 2.0 interface for data transfers and firmware updates. The JMF612 has an ARM9 embedded processor with 32KB of ROM and 128KB of RAM at its core. Data integrity is provided by BCH ECC in hardware, with the ability to correct up to 24 random bit errors per 1024 bytes. Dynamic and static wear leveling technologies, along with updated bad block management software help to ensure long life of the drive.
The first terabyte SSDs on the market could end up using this controller chip. It uses eight memory channels to access its storage quickly and without lag.
JMicron will be showing engineering samples of its latest controller at Computex 2009 at the beginning of June. Mass production of the new chip is expected to start in July. The company is also working on a flash controller that will work at SATA 6Gbps speeds, but it is not expected to be ready for mass production until the middle of 2010.