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50nm lowers cost and power consumption

New 50nm DDR3 DIMMs from Samsung and Elpida are entering mass production this month. The chips will feature higher densities and speeds while lowering latencies, power consumption, and costs.

Elpida's new 50nm process uses 193nm argon fluoride immersion lithography combined with copper interconnect technology, providing a 25 percent speed boost over standard aluminum interconnects. A standard chip size of less than 40mm2 means that there will be more dies produced per wafer, lowering costs once the line matures and yields are maximized.

The new chips are capable of 2.5Gb/s at a standard 1.5v, but can also be used at 1.2v up to 1.6Gb/s. Initial production will be at 1Gb densities. This enables new usage models in the mobile and server application space.

Corsair's Dominator GT 2GHz CL7 DDR3 DIMMs were shown at CES, and they may enter production this month using Elpida's latest.

Meanwhile, the world's only profitable DRAM producer is not standing still.

Samsung's own 50nm process is being used to manufacture 2Gb DDR3, and is expected to become Samsung's primary DRAM process technology this year. They claim a 60% increase in productivity over their DDR2 equivalents.

Qimonda taped out its 46nm DDR3 Buried Wordline technology in November, ahead of their internal schedule. They hope to start mass production by mid 2009.

Many other DDR3 producers are also looking to lower geometries in preparation for AMD's AM3 socket launch and Intel's Lynnfield launch, both of which will use DDR3 and accelerate market demand.

The price premium of DDR3 could drop from 100% to 10% by the time Lynnfield and Windows 7 launch together in Q3. Intel will be using DDR3 exclusively on its 32nm Westmere CPUs.

Due to a massive glut of DDR2 chips, there are almost no plans to upgrade factories to 50nm for DDR2. Instead, they will transition to surplus 65nm and 70nm equipment currently used for DDR3.

According to International Data Corporation, an IT market research firm, DDR3 sales will account for 29 percent of the total DRAM market by units sold in 2009. This will grow to 72 percent in 2011.

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RE: Faster memory? Meh...
By ekv on 1/20/2009 2:32:01 PM , Rating: 2
Usually we talk about memory 'bandwidth' and memory 'latency'. Bandwidth can be had in adbundance, it just takes a little longer to achieve. Think of a firehose, from when you turn it on till it's pouring out is not instantaneous, but when it arrives, oy! meshugge!

Latency is the harder of the two. It is why most microprocessor makers have layers of cache designed into their memory hierarchy. L1 cache is very "fast", in this case read "low-latency and high-bandwidth". The trade-off is that it is expensive and hence its size is limited. L2 cache typically has higher latency than L1, is not as expensive and hence has a larger size. And so on. There are lots of other tricks to hide latency.

When the Sandia study on multiple cores is taken into account -- which is a factor in why Amdahl's law works, if memory serves me -- you have various cores stepping on each other's cache. The more cores the worse the problem. Having a really, really large cache somewhat mitigates this. I recall reading over at EETimes, about 2 years ago, that IBM developed a 48MB dram based memory that fit in the size of a typical on-chip microprocessor cache and was nearly as "fast" (as an sram memory, where dram has higher bit density, by, like, over double). I thought at the time, and posted such, that it would've been a slam dunk for AMD to license the technology from IBM. Hey, AMD, why didn't you knuckleheads ask me about this? 8)

[Good thing Hector is hasta-la-vista-baby].

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