While quantum computers and fiber optic computers are certainly ideal candidates for a silicon PC replacement, they remain in the distant future. In the meantime, one key unexploited domain, which may give silicon a stay of retirement, is 3D chip technologies.
Today virtually all chips on the market are flat, two dimensional designs. While this is somewhat efficient from a cooling perspective, it offers definite limitations in terms of computing resources per given space. A 3D chip could theoretically be much more compact, while being equally efficient. This would have the added perk that it could reduce defects, as larger dies typically lead to more defects. It would also limit propagation delays by shortening interconnects and make the chip harder to reverse engineer.
While some chips designs have claimed to be "3D", most of these designs are merely stacked chips with a few communications interconnects and not mass interoperation between stacked layers. Now the University of Rochester has demoed perhaps the first true 3D processor design. The chip is optimized in 3 dimensions and runs at a speedy 1.4 GHz. Its unique design allows it to become the first chip to offer full functionality in three dimensions in tasks involving synchronicity, power distribution, and long-distance signaling.
"I call it a cube now, because it's not just a chip anymore. This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2-D chip," stated Eby Friedman, Distinguished Professor of Electrical and Computer Engineering at Rochester and faculty director of the processor.
Professor Friedman worked with engineering student Vasilis Pavlidis to develop the design. He says that while Moore's Law of transistors in a given chip area doubling with time may come to halt in a 2 dimensional world, as some are suggesting, extending processors into 3 dimensions will allow it to continue as fast as ever.
The hardest part according to the researchers is getting the levels of the chip to properly interact. Professor Friedman compares the problem to a scenario where a standard microprocessor is like the U.S. traffic system, and then the 3D processor is like 3 or more U.S. traffic systems stacked atop each other and expected to coordinate traffic between levels. He says the problem is even tougher as the processors are different, so it’s more like stacking the U.S., China, and India, where traffic laws are different, atop each other.
However, the advantages are the special purpose processors designed for functions like MP3 encoding could be achieved on a particular layer. Professor Friedman predicts that a 3D processor in a device such as the iPod could be tenth the current processor's size with ten times the speed.
While the chip uses many standard processor design tricks, it also uses new ones to account for different impedances that might occur from chip to chip, different operating speeds, and different power requirements. It is also was uniquely manufactured at MIT, through a technique in which millions of holes were drilled in the insulation between layers, allowing virtually every transistor to be connected, if desired, with those above or below it.
The future, Professor Friedman says is vertical. He states, "Are we going to hit a point where we can't scale integrated circuits any smaller? Horizontally, yes. But we're going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that."
quote: ...many standard processor design tricks, it also uses new ones to account for different impedances that might occur from chip to chip...
quote: Professor Friedman predicts that a 3D processor in a device such as the iPod could be tenth the current processor's size with ten times the speed.
quote: IBM has done some 3D-ICs in the past as well.